I designed the circuit in Figure 1 as a part of a data transmission system that has a carrier frequency of 400 kHz using on-off keying (OOK) modulation.

I needed to detect the presence of the carrier by distinguishing it from other signals of different frequencies. It was converted to digital with a 5-V logic. I wanted to avoid using programmable devices and timers based on RC circuits.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The resulting circuit is made up of four chips, including a crystal time base. In brief, this system measures the time between the rising edges of the received signal on a cycle-by-cycle basis. Thus, it detects if the incoming signal is valid or not in a short time (approximately one carrier cycle, that is ~2.5 µs). This is done independently of the signal duty cycle and in less time than other systems, such as a phase-locked loop (PLL), which may take several cycles to detect a frequency.

Figure 1 A digital frequency divider circuit that detects the presence of a 400-kHz carrier, distinguishing it from signals of other frequencies, after it has been converted to digital using 5-V logic.

How it works

In the schematic, IC1A and IC1B are the 6.144 MHz crystal oscillator and a buffer, respectively. For X1, I used a standard quartz crystal salvaged from an old microprocessor board.

The flip-flops IC2A and IC2B are interconnected such that a rising edge at the IC2A clock input (connected to the signal input) produces, through its output and IC2B input, a low logic level at IC2B Q output. Immediately afterwards, the low logic level resets IC2A, thereby leaving IC2B ready to receive a rising edge at its clock input, which causes its Q output to return to high again. Since the IC2B clock input is continuously receiving the 6.144 MHz clock, the low logic level at its output will have a very short duration. That very narrow pulse presets IC3, which takes its counting outputs to “0000”.

If IC4A is in a reset condition, that pulse will also set it in the way explained below, with the effect of releasing IC4B by deactivating its input (pin 4 of IC4) and enabling IC3 by pulling its input low.

From that instant, IC3 will count the 6.144 MHz pulses, and, if the next rising edge of the input signal occurs when IC3’s count is at “1110” or “1111”, IC1C’s output will be at a low level, so the IC4B output will go high, indicating that a cycle with about the correct period (2.5µs) has been received. Simultaneously, IC3 will be preset to start a new count. If the next rising edge occurred when the IC3 count was not yet at “1110”, IC3 would still be preset, but the circuit output would go low. This last scenario corresponds to an input frequency higher than 400 kHz.

On the contrary, if, after the last rising edge, a longer time than a valid period passes, the functioning of the circuit will be the following. When the IC3 count reaches the value “1111”, a 6.144 MHz clock pulse will occur at the signal input instead of a rising edge. This will make the IC4A Q output take the low level present at the IC3 output and the IC4A data input.

The low level at IC4A Q output will set IC4B, and the circuit output will go low. As IC4A Q output is also connected to its own input, that low level caused by a pulse at its clock input will prevent that flip-flop from responding to further clock pulses. From then on, the only way of taking IC4A out of that state will be by applying a low level (could be a very narrow pulse, as in this case) at its input (pin 10 of IC4). That would establish a forbidden condition for an instant, making IC4A first pull high both Q and , and immediately change to low.

As a result of the circuit logic and timing, after a complete cycle with a period of approximately 2.5 µs is received, the circuit output goes high and remains in that state until a shorter cycle is received, or until a longer time than the correct period elapses without a complete cycle.

Testing the circuit

I tested the circuit with signals from 0 to 10 MHz. The frequencies between 384 kHz and 405 kHz, or periods between 2.47 µs and 2.6 µs, produced a high level at the output. These values correspond to approximately 15 to 16 pulses of the 6.144 MHz clock, being the first of those pulses used to end the presetting of the counter IC3, so it is not counted.

Frequencies lower than 362 kHz or higher than 433 kHz produced a low logic level. For frequencies between 362 kHz and 384 kHz and between 405 kHz and 433 kHz, the circuit produced pulses at the output. That means that for an input period between 2.31 µs and 2.47 µs or between 2.60 µs and 2.76 µs, there will be some likelihood that the output will be in a high or low logic state. That state will depend on the phase difference between the input signal and the 6.144 MHz clock.

Figure 2 shows a five-pulse 400 kHz burst (lower trace), which is applied to the input of the circuit. The upper trace is the output; it can be seen that after the first cycle has been measured. The output goes high, and it stays in that state as more 2.5 µs cycles keep arriving. After a time slightly higher than 2.5 µs without a complete cycle (~2.76 µs), the output goes low.

Figure 2 A five-pulse 400-kHz burst applied to the input of the digital frequency divider circuit (CH2) and the output (CH2) after the first cycle has been measured.

Ariel Benvenuto is an Electronics Engineer and a PhD in physics, and works in research with IFIS Litoral in Santa Fe, Argentina.

Related Content

• Divider generates accurate 455kHz square-wave signal
• Frequency and phase locked loops
• Simplifying PLL Design
• Demystifying the PLL

The post A digital frequency detector appeared first on EDN.