Fan-out wafer-level packaging (FOWLP) is becoming a critical technology in advanced semiconductor packaging, marking a significant shift in system integration strategies. Industry analyses show 3D IC and advanced packaging make up more than 45% of the IC packaging market value, underscoring the move to more sophisticated solutions.

The challenges are significant—from thermal management and testing to the need for greater automation and cross-domain expertise—but the potential benefits in terms of performance, power efficiency, and integration density make these challenges worth addressing.

Figure 1 3D IC and advanced packaging make up more than 45% of the IC packaging market value. Source: Siemens EDA

This article explores the automation frameworks needed for successful FOWLP design and focuses on core design processes and effective cross-functional collaboration.

Understanding FOWLP technology

FOWLP is an advanced packaging method that integrates multiple dies from different process nodes into a compact system. By eliminating substrates and using wafer-level batch processing, FOWLP can reduce cost and improve yield. Because it shortens interconnect lengths, FOWLP packages offer lower signal delays and power consumption compared to conventional methods. They are also thinner, making them ideal for space-constrained devices such as smartphones.

Another key benefit is support for advanced stacking, such as placing DRAM above a processor. As designs become more complex, this enables higher performance while maintaining manageable form factors. FOWLP also supports heterogeneous integration, accommodating a wide array of die combinations to suit application needs.

The need for automation in FOWLP design

Designing with FOWLP exceeds the capabilities of traditional PCB design methods. Two main challenges drive the need for automation: the inherent complexity of FOWLP and the scale of modern layouts, racking up millions of pins and tens of thousands of nets. Manual techniques cannot reliably manage this complexity and scale, increasing the risk of errors and inefficiency.

Adopting automation is not simply about speeding up manual tasks. It requires a complete change in how design teams approach complex packaging design and collaborate across disciplines. Let’s look at a few of the salient ways to make this transformation successful.

1. Technology setup

All FOWLP designs start with a thorough technology setup. Process design kits (PDKs) from foundries specify layer constraints, via spans, and spacing rules. Integrating these foundry-specific rules into the design environment ensures every downstream step follows industry requirements.

Automation frameworks must interpret and apply these rules consistently throughout the design. Success here depends on close attention to detail and a deep understanding of both the foundry’s expectations and the capabilities of the design tools.

2. Assembly and floor planning

During assembly and floor planning, designers establish the physical relationships between dies and other components. This phase must account for thermal and mechanical stress from the start. Automation makes it practical to incorporate early thermal analysis and flag potential issues before fabrication.

Effective design partitioning is also critical when working with automated layouts. Automated classification and grouping of nets allow custom routing strategies. This is especially important for high-speed die-to-die interfaces, compared to less critical utility signals. The framework should distinguish between these and apply suitable methodologies.

3. Fan-out and routing

Fan-out and routing are among the most technically challenging parts of FOWLP design. The automation system must support advanced power distribution networks such as regional power islands, floodplains, or striping. For signal routing, the system needs to manage many constraints at once, including routing lengths, routing targets, and handling differential pairs.

Automated sequence management is essential, enabling designers to iterate and refine routing as requirements evolve. Being able to adjust routing priorities dynamically helps meet electrical and physical design constraints.

4. Final verification and finishing

The last design phase is verification and finishing. Here, automation systems handle degassing hole patterns, verifying stress and density requirements, and integrating dummy metal fills. Preparing data for GDS or OASIS output is streamlined, ensuring the final package meets manufacturing and reliability standards.

Building successful automated workflows

For FOWLP automation flows to succeed, frameworks must balance technical power with ease of use. Specialists should be able to focus on their discipline without needing deep programming skills. Automated commands should have clear, self-explanatory names, and straightforward options.

Effective frameworks promote collaboration among package designers, layout specialists, signal and power integrity analysts, and thermal and mechanical engineers. Sharing a common design environment helps teams work together and apply their skills where they are most valuable.

A crucial role in FOWLP design automation is the replay coordinator. This person orchestrates the entire workflow, managing contributions from all team members as well as the sequence and dependencies of automated tasks, ensuring that all the various design steps are properly sequenced and executed.

To be effective, replay coordinators need a high-level understanding of the overall process and strong communication with the team. They are responsible for interpreting analysis results, coordinating adjustments, and driving the group toward optimal design outcomes.

The tools of the new trade

This successful shift in how we approach microarchitectural design requires new tools and technologies that support the transition from 2D to 3D ICs. Siemens EDA’s Innovator3D IC is a unified cockpit for design planning, prototyping, and predictive analysis of 2.5/3D heterogeneous integrated devices.

Innovator3D IC constructs a digital twin, unified data model of the complete semiconductor package assembly. By using system technology co-optimization, Innovator3D IC enables designers to meet their power, performance, area, and cost objectives.

Figure 2 Innovator3D IC features a unified cockpit. Source: Siemens EDA

FOWLP marks a fundamental evolution in semiconductor packaging. The future of semiconductor packaging lies in the ability to balance technological sophistication with practical implementation. Success with this technology relies on automation frameworks that make complex designs practical while enabling effective teamwork.

As industry continues to progress, organizations with robust FOWLP automation strategies will have a competitive advantage in delivering advanced products and driving the next wave of semiconductor innovation.

Todd Burkholder is a Senior Editor at Siemens DISW. For over 25 years, he has worked as editor, author, and ghost writer with internal and external customers to create print and digital content across a broad range of EDA technologies. Todd began his career in marketing for high-technology and other industries in 1992 after earning a Bachelor of Science at Portland State University and a Master of Science degree from the University of Arizona.

Chris Cone is an IC packaging product marketing manager at Siemens EDA with a diverse technical background spanning both design engineering and EDA tools. His unique combination of hands-on design experience and deep knowledge of EDA tools provides him with valuable insights into the challenges and opportunities of modern semiconductor packaging, particularly in automated workflows for FOWLP.

Editor’s Notes

This is third and final part of the article series on 3D IC. The first part provided essential context and practical depth for design engineers working on 3D IC systems. The second part highlighted 3D IC design toolkits and workflows to demonstrate how the integration technology works.

Related Content

• 3D IC Design
• Thermal analysis tool aims to reinvigorate 3D-IC design
• Heterogeneous Integration and the Evolution of IC Packaging
• Tighter Integration Between Process Technologies and Packaging
• Advanced IC Packaging: The Roadmap to 3D IC Semiconductor Scaling

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