The RISC-V Summit North America, held on 22-23 October 2025 in Santa Clara, California, showcased the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems. These CPU cores were accompanied by reference boards, software design kits (SDKs), and toolchains.

The show also provided a sneak peek of the RISC-V’s design ecosystem, which is maturing fast with the RVA23 application profile and RISC-V Software Ecosystem (RISE), a Linux Foundation project. The emerging ecosystem encompasses compilers, system libraries, language runtimes, simulators, emulators, system firmware, and more.

“The performance gap between high-end Arm and RISC-V CPU cores is narrowing and a near parity is projected by the end of 2026,” said Richard Wawrzyniak, principal analyst for ASIC, SoC and IP at The SHD Group. He named Andes, MIPS, Nuclei Systems, and SiFive as market leaders in RISC-V IP. Wawrzyniak also mentioned new entrants such as Akeana, Tenstorrent, and Ventana.

Andes, boasting 20 years of expertise in the semiconductor IP business, was a prominent presence in the corridors of the RISC-V Summit in Santa Clara. It’s a founding member of RISC-V International and a pure-play IP vendor. At the RISC-V Summit, Andes displayed its processor lineup, including AX45, AX46, AX66, and Cuzco.

Figure 1 The processor lineup was showcased at the RISC-V Summit in Santa Clara. Source: Andes

Andes claims that these RISC-V processors, featuring powerful compute and efficient control, provide the architectural diversity required in artificial intelligence (AI) applications. AX45 and AX46 processors have been taped out and are shipping in volumes. Here, Andes also provides in-chip firmware, tester software, on-board software, and on-cloud software as part of its hardware IP monitoring offerings.

Though RISC-V is enjoying a robust deployment in automotive, Internet of Things (IoT), and networking, AI was all the rage on the RISC-V Summit floor. “If RISC-V has a tailwind, it’s AI,” Wawrzyniak said.

RISC-V world’s AI moment

Andes claims it’s driving RISC-V into the AI world with features such as advanced vector processing. And that its RISC-V processors are powering devices from the battery-sipping edge to high-performance data centers. Andes also claims that 38% of its revenue comes from AI designs.

Companies like Andes can also bring differentiation and efficiency to AI processor designs through automated custom extensions. “We are getting there, and the deployment speed is impressive,” said Dr. Charlie Su, president and CTO of Andes Technology.

Figure 2 Meta deployed two generations of AI accelerators for training and inference using RISC-V vector/scalar cores. Source: Andes

“RISC-V is getting better for AI applications in data centers,” said Ty Garibay, president of Condor Computing. “RVA23 has a massive investment in features for data center-class AI designs.” Condor Computing, a wholly owned subsidiary of Andes, founded in 2023, develops high-performance RISC-V IPs and is based in Austin, Texas.

Wawrzyniak of SHD Group acknowledges that AI applications are driving the adoption of RISC-V-enabled system-on-chips (SoCs). “The heterogeneous nature of SoCs has created opportunities for multiple CPU architectures,” he said. “These SoCs can support both RISC-V and other ISAs, allowing applications to pick the best core for each function.”

Moreover, the diverse needs for AI acceleration are fueling the demand for RISC-V. “RISC-V CPU IP vendors can more easily introduce new and more powerful CPU cores, which extends the reach of RISC-V into AI applications that require greater compute power,” Wawrzyniak said.

During his keynote, Wawrzyniak said that initial RISC-V deployments were driven by embedded applications such as networking, smart sensors, storage, and wearables. “RISC-V is now transitioning to higher-end applications like ADAS and data centers as AI expands to those applications.”

RISC-V processor duo

At the RISC-V Summit, Andes provided more details about its new application processors. It showcased AX66, a mid-range application processor, and Cuzco, a high-end application processor; both are RVA23-compliant. AX66—incorporating up to 8 cores—features dual vector pipes with VLEN=128 and front-end decode 4-wide. It has a shared L3 cache of up to 32 MB.

Figure 3 AX66 is a 64-bit multicore CPU IP for developing a high-performance quad-decode 13-stage superscalar out-of-order processor. Source: Andes

On the higher end, Cuzco features time-based scheduling with a time resource matrix to determine instruction issue cycles after decoding, thereby reducing logic complexity and dynamic power for wide machines. Cuzco’s decode is either 6-wide or 8-wide, and it has 8 execution pipelines (2 per slice).

Cuzco incorporates up to 8 cores and offers a shared L3 cache of up to 256 MB. The Cuzco RISC-V processor has been implemented at 5-nm nodes with 8 execution pipelines and 7 million gates. It features an L2 configuration with 2MB and is targeted for a 2.5-GHz speed.

Figure 4 The Cuzco design represents the first in a new class of RISC-V CPUs aimed at data center-class performance while maintaining power efficiency and area benefits. Source: Andes

For the development of these RISC-V processors, the AndeSight integrated development environment (IDE) helps design engineers generate files for LLVM to recognize new instructions. Then there is AndesAIRE software, which facilitates graph-level optimization for pruning and quantization as well as back-end-aware optimization for fusion and allocation.

For OS support, the processors comply with RVA22 and RVA23 profiles and SoC hardware and software platforms. Andes also provides additional support to ensure that the Linux kernel is upstream-compatible.

Cuzco, unveiled at Hot Chips 2025 earlier this year, features a time-based out-of-order microarchitecture engineered to deliver high performance and efficiency across compute-intensive applications in AI, data center, networking, and automotive markets. Andes provided a preview of this out-of-order CPU at the RISC-V Summit.

Condor Computing developed the Cuzco RISC-V core, which is fully integrated into the Andes toolchain and ecosystem. Condor recently completed full hardware emulation of its new CPU IP while successfully booting Linux and other operating systems.

“Condor’s microarchitecture combines advanced out-of-order execution with novel hardware techniques to dramatically boost performance-per-watt and silicon efficiency,” Andes CTO Su said. “It’s ideally suited for demanding CPU workloads in AI, automotive compute, applications processing, and beyond.”

The first customer availability of the Cuzco RISC-V processor is expected in the fourth quarter of 2025.

The RISC-V adoption

According to Wawrzyniak, chip designers are now looking at both Arm and RISC-V processor architectures. “The RISC-V ISA and its rising ecosystem have interjected competition once again into the SoC design landscape.”

Furthermore, the custom RISC-V ISA extensions empower innovation and tailored performance. Not surprisingly, therefore, the adoption of RISC-V by large technology companies such as Broadcom, Google, Meta, MediaTek, Qualcomm, Renesas, and Samsung continues to validate the utility of the RISC-V ISA in the semiconductor industry.

RISC-V, once an academic exercise, has come a long way since its launch in May 2010 at the University of California, Berkley. However, as Krste Asanovic, chief architect at SiFive, said during his keynote, RISC-V will continue to evolve across different verticals and that it’ll be around for a long time.

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