Introduction

I am really enjoying designing hardware at the moment. We have recently created the AMD Spartan™ 7 FPGA Embedded System Tile and the Tile Carrier Card. In this project, we are going to look at the concept and architecture for a tile based on the AMD Spartan UltraScale+™ FPGAs.

The current Spartan 7 FPGA Tile and carrier card can be seen below.

The idea is that this Spartan UltraScale+ FPGA Tile will be compatible with the Tile Carrier Card for design prototyping, and can be designed into your solution directly.

The thought process behind this is that I want to create a tile that is able to offer a higher performance solution with increased logic capabilities, transceivers, high-performance memories, and updated security.

Requirements

The Spartan UltraScale+ FPGA Tile shall have the following requirements:

REQ001 - The Spartan UltraScale+ FPGA Tile shall be capable of supporting the SU10P to SU50P devices in a SBVB625 footprint.

REQ002 - The tile shall be pin compatible with the tile carrier pin out.

REQ003 - The tile shall provide a separate output for the transceiver.

REQ004 - The form factor shall be the same as the existing Spartan 7 FPGA Tile.

REQ005 - The tile shall provide QSPI non-volatile configuration memory.

REQ006 - The tile shall provide JTAG interface for programming.

REQ007 - The tile shall provide a FDTI Interface which provides USB JTAG and three USB UARTS.

REQ008 - Configuration of the FPGA shall be selectable between the NVRAM and JTAG.

REQ009 - The tile shall provide a 100 MHz clock for logic.

REQ010 - The tile shall provide a programmable clock generator.

REQ011 - The tile shall provide I2C programming of the clock generator from either the FPGA or from a remote header.

REQ012 - The tile shall operate from a single power supply with input range 4.5 to 18V.

REQ013 - The tile shall provide at one done LED, and two user LEDs.

REQ014 - The tile shall provide at least two user push buttons.

REQ015 - The tile should provide a 6-axis accelerometer.

REQ016 - The tile should provide a digital barometer.

REQ017 - The tile should provide a PM bus connection if PMICs are used.

REQ018 - The tile should provide access to the Sysmon.

REQ019 - The tile shall provide HyperRAM or other such memory to enable larger program execution e.g. AMD MicroBlaze™ V processors.

REQ020 - The power dissipation of the module shall be monitorable.

Architecture

With a set of requirements to examine, we are able to develop an architectural concept for the tile.

This drops pretty straightforward from the requirements, however there are some derived requirements. The main one being the inclusion of an I2C header for access to the barometer, accelerometer and power monitor. This will enable access during bring up of the board.

The I2C access also enables a remote master to be able to remotely monitor the power consumption. This can be useful during board bring up and during prototyping applications where we want to be able to monitor the power which is being taken by algorithms implemented. This I2C header will also connect to the Sysmon I2C to enable access to the Sysmon registers.

Configuration

The tile will be able to configure the FPGA from either a non-volatile Quad SPI or JTAG.

To ensure we have sufficient storage for the uncompressed PL image, we need to ensure we can store at least 15.7 Mbits.

Power

The next step in the design of the concept is to identify the power supplied needed. AMD UltraScale+ devices require several different voltages rails to power the core, auxiliary rails and the IO voltages for the IO banks.

VCCINT — Core fabricDrives the programmable logic itself: LUTs, routing, DSP, control/state machines, typical UltraScale+ device voltages are 0.85. This is one of the rails that might require a high current dependent on the application demands.

VCC_Int_IO — Internal I/O supportThis is an internal supply for HP and XP5IO I/O banks.

VCCBRAM — Block RAM arraysSupply voltage for the block RAM and UltraRAM - This must be connected to VCC_Int_IO.

VCCAUX — Auxiliary/configurationThe global auxiliary (VCCAUX) supply rail primarily provides power to the interconnect logic of the various blocks inside the device.

VCCAUX_HDIO / HPIO / XPIO — Auxiliary/configurationThe auxiliary I/O (VCCAUX_HDIO, VCCAUX_HPIO, and VCCAUX_XP5IO) voltage supply rail provides power to the I/O circuitry.

VCCADC — System Monitor analogSystem Monitor supply.

VCCIO — HP bank I/O levelsPer-bank rail for HP banks, which support low-voltage standards (≤ 1.8 V) and high-speed interfaces. Set this to match your chosen I/O standard (e.g., 1.2/1.5/1.8 V SSTL, low-swing LVDS). You can’t run 3.3 V here.

VCCIO — HD bank I/O levelsPer-bank rail for HD banks, which support general-purpose single-ended I/O up to 3.3 V. Set this to the external interface requirement (e.g., 3.3 V for GPIO, 2.5 V for certain peripherals).

I have used Power Design Manager to size the power solution. To account for the worst-case power dissipation, I used every logic, DSP, BRAM resource within the device and selected a 500MHz clock frequency.

Power Design Manager provides us with the ability to select FPGA resources and their clock rate.

The summary of the power requirements identified by the power design manager is shown below.

Power design manager also shows the breakdown of power by rail.

Power Sequencing

To ensure the FPGA powers on taking minimal current and the IOs are correctly tri-stated at power on, there is a recommended power sequence, which is VCCINT, VCCINT_IO/VCCBRAM, VCCAUX/VCCAUX_IO, and VCCO.

When it comes to powering down, it is recommended to reverse the power sequence e.g. VCCO, then VCCAUX/VCCAUX_IO, VCCINT_IO/VCCBRAM and VCCINT.

We also need to be able to ensure the power solution is able to achieve the power on current requirements shown in the table below.

Power Architecture

Having understood the requirements for the power solution, we are able to create a power architecture. This architecture shows the rails which can be shared. I have tried to minimize the number of different rails required.

I have combined the VCC_INT_IO and VCC_BRAM as recommended by the data sheet. I have also combined VCCAUX and VCCAUX_HD as both need 1v8. However, I have kept the VCCAUX_HP fail which also needs 1v8 on its own supply.

To maintain compatibility with the existing tile, the majority of the IO will be 3v3, however, one bank will be user selectable via VCCO pins presented to the IO Ring.

To ensure the sequencing is correct, the power outputs will be used to sequence the supplies. The power good from the first rails to power will be connected to the enables of the next stages power regulator.

Clock Architecture

The clocking architecture on the tile will be the straightforward with a 100 MHz clock being supplied into one on of the fourteen global clock inputs supplied on the FPGA.

To provide the user with flexible clocking at different frequencies, the tile should also provide three programmable clocks.

Clocking resources are split between HD and HP banks on the Spartan UltraScale+ FPGA. Each IO bank has four clock capable pins, capable of supporting single or differential signals.

Global clocks in HDIO can only drive directly BUFG and not MMCM / PLL. They must be routed to the MMCM/PLL to be used first, if desired.

For this project, both the fixed oscillator and programable oscillator will be connected to HDIO banks.

Additionally, spare global clocks from the HDIO used in the IO ring will be provided to enable access to clocking resources from the wider system design.

I2C Architecture

The design will have two I2C networks. The first will be connected to the FPGA and an external interface, allowing master access from either. This I2C network is designed to provide information on the environment of the tile. This enables access to the accelerometer, barometer, FPGA Sysmon and current monitor.

The second I2C network is dedicated for the programmable clocking oscillator.

Component Selection

When developing the tile, we need to identify all of the major components that we wish to use in the design.

The major components, including FPGA, memories, clocks, environmental sensors, and power supplies are identified in the table below.

Compliance Matrix

This project has demonstrated how I will implement the requirements provided at the start. I think the solution is fully implemented, however, it is good practice to perform a compliance matrix.

The largest technical risk the project faces is being able to fit the FPGA and associated requirements on to board area the size of the Spartan 7 FPGA tile, which is 59 mm by 59 mm.

Next Steps

The schematics for this are in progress, along with some early 3D models you can see in the project.

I am quite excited by this development, as it will provide for a small, high-performance tile which is also very power efficient. It will also provide a very interesting range of products!

Reference Material

The following AMD Spartan™ UltraScale+™ FPGA documentation came in useful when developing this board.

Data Sheet

Select IO User Guide

Pin Descriptions

AMD sponsored this project, including engineering hours. AMD, and the AMD Arrow logo, Microblaze, Spartan, UltraScale+, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.