Researchers from Intel, in collaboration with researchers at Georgia Institute of Technology designed a new SOT-MRAM device at 7 nm. This work spans the entire project range, from device-level characteristics to system-level power performance area.
Based on ASAP7 PDK design rules, the researchers created the bit-cell and peripheral layout...
Researchers from Intel, in collaboration with researchers at Georgia Institute of Technology designed a new SOT-MRAM device at 7 nm. This work spans the entire project range, from device-level characteristics to system-level power performance area.
Based on ASAP7 PDK design rules, the researchers created the bit-cell and peripheral layouts for SOT-MRAM and designed the entire array. Based on place and route, the system-level PPA was calculated for various memory capacities, demonstrating bit-densities up to 14.8 Mb/mm2 and read bandwidths up to 2.98 GB/s.