AMD on Tuesday unveiled its future "Zen 7" CPU microarchitecture. The company has been pivoting toward making its CPU IP more AI-relevant, so future processing workloads could better leverage the serial processing power of CPUs. Among these, the two important ones are AVX10 and ACE. AVX10 sees a unification of AVX-512 and AVX2 features to improve performance and compatibility across vector math heavy workloads. ACE, or Advanced Matrix Extensions for Matrix Manipulation, is an industry-standard matrix math instruction set that could prove to be relevant to every device ranging from smartphones to servers.
Among the other ISA …
AMD on Tuesday unveiled its future "Zen 7" CPU microarchitecture. The company has been pivoting toward making its CPU IP more AI-relevant, so future processing workloads could better leverage the serial processing power of CPUs. Among these, the two important ones are AVX10 and ACE. AVX10 sees a unification of AVX-512 and AVX2 features to improve performance and compatibility across vector math heavy workloads. ACE, or Advanced Matrix Extensions for Matrix Manipulation, is an industry-standard matrix math instruction set that could prove to be relevant to every device ranging from smartphones to servers.
Among the other ISA additions with Zen 7 are FRED (flexible return and event delivery), which replaces the current device interrupt model to reduce system-level latency. Zen 7 also implements ChkTag x86 Memory Tagging to counteract several kinds of memory-level data vulnerabilities caused by buffer overflows and use-after-free errors. FRED in particular was a noteworthy feature Intel was working on for its x86S machine architecture standard.
