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CPU Architecture
🏗️ CPU Architecture
Pipeline Design, Branch Prediction, Cache Hierarchies, Superscalar
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The Tick-Tock AI Development Cycle.
🧠
Memory Management
wilsoniumite.com
·
17h
17 hours ago
Actions for The Tick-Tock AI Development Cycle.
uiCA: Accurate Throughput
Prediction
of Basic Blocks on Recent Intel
Microarchitectures
⚙️
Compilers
Content type:
Academic
arxiv.org
·
1d
1 day ago
·
Hacker News
Actions for uiCA: Accurate Throughput Prediction of Basic Blocks on Recent Intel Microarchitectures
How much do amd64
microarchitecture
levels help in Go?
🔩
Assembly
Content type:
Blog
lemire.me
·
4d
4 days ago
·
Lobsters
,
Hacker News
,
r/golang
Actions for How much do amd64 microarchitecture levels help in Go?
Intel 8086, the First x86 chip, Enters its 50th Year in 2027
🔬
RISC-V
techpowerup.com
·
1d
1 day ago
Actions for Intel 8086, the First x86 chip, Enters its 50th Year in 2027
Why x86 Zeroes a
Register
With `xor eax, eax`
⚙️
Compilers
Content type:
Blog
debasishg.github.io
·
3d
3 days ago
Actions for Why x86 Zeroes a Register With `xor eax, eax`
Apple Chip
Architecture
from 1977 to 2026
💻
Computer Hardware
Content type:
News
Content type:
Blog
blog.jacobstechtavern.com
·
1d
1 day ago
Actions for Apple Chip Architecture from 1977 to 2026
New OS kernel uncovers hidden Apple M1 behavior and possible Phantom attack
🖥️
Operating Systems
techxplore.com
·
12h
12 hours ago
Actions for New OS kernel uncovers hidden Apple M1 behavior and possible Phantom attack
Graviton5’s improved
design
increases speed and energy efficiency — beyond Moore’s law
💻
Computer Hardware
Content type:
Blog
amazon.science
·
18h
18 hours ago
·
Hacker News
Actions for Graviton5’s improved design increases speed and energy efficiency — beyond Moore’s law
Exploiting GPU Tensor Cores from Java using Babylon [Juan Fumero]
🎮
GPU Programming
openjdk.org
·
2d
2 days ago
·
r/java
Actions for Exploiting GPU Tensor Cores from Java using Babylon [Juan Fumero]
Error Handling in Rust vs. Exceptions in other languages
🦀
Rust
slicker.me
·
5h
5 hours ago
·
r/rust
Actions for Error Handling in Rust vs. Exceptions in other languages
Simplifying Weak Reference Processing in ZGC
🧠
Memory Management
inside.java
·
10h
10 hours ago
Actions for Simplifying Weak Reference Processing in ZGC
The copy_if Speedup That Wasn't About copy_if, Or AVX-512
🔢
SIMD
hftuniversity.com
·
6d
6 days ago
·
Substack
Actions for The copy_if Speedup That Wasn't About copy_if, Or AVX-512
Less-relevant results
ARM MTE & Apple MIE: How Hardware Memory Tagging Reveals Invisible iOS Kernel Vulnerabilities
🖥️
Operating Systems
Content type:
Blog
jamf.com
·
20h
20 hours ago
Actions for ARM MTE & Apple MIE: How Hardware Memory Tagging Reveals Invisible iOS Kernel Vulnerabilities
Founding Engineer - FPGA, RTL, & ASIC
Architect
at Zettascale
🔧
FPGA
ycombinator.com
·
6d
6 days ago
·
Hacker News
Actions for Founding Engineer - FPGA, RTL, & ASIC Architect at Zettascale
Sequential hardness of a MUL-XOR-shift permutation: open questions
🔧
FPGA
Content type:
Code
github.com
·
2d
2 days ago
·
r/crypto
Actions for Sequential hardness of a MUL-XOR-shift permutation: open questions
Fractal OS Lets Security Researchers See What Their CPUs Really Do
🖥️
Operating Systems
Content type:
News
spectrum.ieee.org
·
1d
1 day ago
Actions for Fractal OS Lets Security Researchers See What Their CPUs Really Do
The last bit – Part 3
⚙️
Compilers
thinkingeek.com
·
5d
5 days ago
Actions for The last bit – Part 3
Dew Drop - June 8, 2026 (#4685)
🖥️
Operating Systems
alvinashcraft.com
·
2d
2 days ago
Actions for Dew Drop - June 8, 2026 (#4685)
Aging
Mice
Became Stronger When Scientists Boosted One Protein
⌨
Programming
sciencealert.com
·
5d
5 days ago
Actions for Aging Mice Became Stronger When Scientists Boosted One Protein
AMD Ryzen 9 9950X3D2 Dual Edition Review - Maximum
Cache
🔩
Assembly
techpowerup.com
·
1d
1 day ago
·
r/hardware
Actions for AMD Ryzen 9 9950X3D2 Dual Edition Review - Maximum Cache
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