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🔬 RISC-V
Open Hardware, Instruction Sets, CPU Design, SiFive
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82416
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274.4
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The Launch of
RISC-V
Now! A New
Chapter
in Open Computing
semiwiki.com
·
4d
🖥️
Operating Systems
System-Level Isolation for
Mixed-Criticality
RISC-V
SoCs
: A "World" Reality Check
arxiv.org
·
2d
🔧
FPGA
MicroBlaze
MCS Seven-Segment Counter on
Basys
3 FPGA
hackster.io
·
1d
🔧
FPGA
Heterogeneous
Processing: A Strategy for
Augmenting
Moore's Law (2006)
linuxjournal.com
·
3h
·
Discuss:
Hacker News
🔢
SIMD
Hardware
Acceleration
jellyfin.org
·
20h
💻
Computer Hardware
CVA6-CFI
: A First Glance at RISC-V Control-Flow Integrity Extensions
arxiv.org
·
2d
⚡
Zig
Last Week on My Mac: Why E
cores
make Apple
silicon
fast
eclecticlight.co
·
8h
·
Discuss:
Hacker News
,
r/hardware
🖥️
Operating Systems
Portable
C
Compiler
en.wikipedia.org
·
16h
·
Discuss:
Hacker News
⚙️
Compilers
Concurrency
Deep Dive: Memory Models, Lock-Free, and
RCU
dev.to
·
1d
·
Discuss:
DEV
🔀
Parallel Algorithms
Intel Appears To Have Quietly
Sunset
"On Demand" Software
Defined
Silicon
phoronix.com
·
4h
🖥️
Operating Systems
NixOS: Systemd unit-linking script rewrite for 60x
speedups
by
Profpatsch
· Pull Request #479442
github.com
·
1d
·
Discuss:
Hacker News
📦
NixOS
Ubuntu on
RISC-V
might actually be good
thanks
to this chip
howtogeek.com
·
2d
🎨
Vulkan
More
cores
didn't improve my
workflow
xda-developers.com
·
17h
🔢
SIMD
Apple’s
M5
strategy points to
unified
chip design
igorslab.de
·
11h
🔧
FPGA
Hello Edge: Keyword
Spotting
on
Microcontrollers
paperium.net
·
1d
·
Discuss:
DEV
🏗️
CPU Architecture
Announcing
TCMalloc
abseil.io
·
18h
🧠
Memory Management
I Built a 6
BIPS
JIT
in Five Months
unlikelyemphasis.substack.com
·
2d
·
Discuss:
Substack
🧠
Memory Management
Unlocking core memories with
GoldSrc
engine and
CS
1.6 (2025)
danielbrendel.com
·
4h
·
Discuss:
Hacker News
🦀
Rust
Upgrading
An Old Macbook With an Old
Processor
hackaday.com
·
7h
💻
Computer Hardware
This industrial cooling setup keeps AMD's $12,000 96-core
Threadripper
Pro
9995WX
cool at 5.3 GHz
techspot.com
·
2h
🏗️
CPU Architecture
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