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🏗️ CPU Architecture
Pipeline Design, Branch Prediction, Cache Hierarchies, Superscalar
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121830
posts in
2.27
s
Testing a 6200 and
comparison
with 6100
68kmla.org
·
2d
🧠
Memory Management
Understanding the Go
Runtime
: The
Bootstrap
internals-for-interns.com
·
3d
·
Discuss:
Hacker News
,
r/golang
⚡
Zig
The Risk of Not
Optimizing
Clock
Power
semiwiki.com
·
5d
🔬
RISC-V
I got tired of
copying
AI output between tools, so I built a system to keep context
intact
miniloop.ai
·
1d
·
Discuss:
DEV
⚡
Zig
Sponsored
: The evolving AI data center: Options
multiply
, constraints grow, and infrastructure planning is even more critical
datacenterdynamics.com
·
1d
⚡
Zig
"
Recursive
Self-Improvement
" Is Three Different Things
lesswrong.com
·
1d
🔧
FPGA
not much
happened
today
news.smol.ai
·
3d
🧠
Memory Management
AMD's open-source
openSIL
firmware is being ported to Zen 5 motherboard early — replacement for
AGESA
shows up ahead of Zen 6
tomshardware.com
·
1d
🔬
RISC-V
Notes on using AI tools for debugging, learning, and shipping software (as a
cautious
adopter
)
linkedin.com
·
1d
·
Discuss:
r/programming
📊
Performance Tools
More
cores
didn't improve my
workflow
xda-developers.com
·
4d
🔢
SIMD
The Next Great Engineering
Frontier
: The Hidden
Complexity
of Physical AI
hackernoon.com
·
1d
🔧
FPGA
John
Carmack
muses
using a long fiber line as as an L2 cache for streaming AI data — programmer imagines fiber as alternative to DRAM
tomshardware.com
·
2d
·
Discuss:
Hacker News
🧠
Memory Management
Massive
leak
details Intel's 900-series Nova Lake
chipset
techspot.com
·
2d
💻
Computer Hardware
Is Local
Hardware
Is All You Need?
wwws.nightwatchcybersecurity.com
·
1d
·
Discuss:
Hacker News
💻
Computer Hardware
AndPuQing/gflow
: A lightweight, single-node GPU job scheduler implemented in Rust.
github.com
·
19h
·
Discuss:
Hacker News
🎨
Vulkan
Performance Tip of the Week #53: Precise C++ benchmark
measurements
with Hardware Performance
Counters
abseil.io
·
4d
📊
Performance Tools
Running a Low Power AI Server 24/7
dev.to
·
1d
·
Discuss:
DEV
💻
Computer Hardware
Series-Parallel-Loop
Decompositions
of Control-flow Graphs
arxiv.org
·
2d
🔀
Parallel Algorithms
Information Flow Verification Framework
Integrating
Static and
Formal
Verification Methods At The Pre-Silicon Stage (U. of Florida)
semiengineering.com
·
1d
⚡
Zig
baochip/baochip-1x
:
Baochip
1x
Silicon
github.com
·
16h
🔧
FPGA
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