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🔬 RISC-V
Open Hardware, Instruction Sets, CPU Design, SiFive
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112081
posts in
462.4
ms
A
RISC-V
vector
extension primer
blog.adafruit.com
·
23h
🔢
SIMD
RISC-V
Pivots
from Academia to Industrial
Heavyweight
eetimes.com
·
1d
🏗️
CPU Architecture
xorvoid/sectorc
: A C Compiler that fits in the 512 byte boot sector of an x86 machine
github.com
·
13h
🔩
Assembly
Benchmarking for Single Feature Attribution with
Microarchitecture
Cliffs
arxiv.org
·
10h
🏗️
CPU Architecture
[Development] 4MB 32-bit
SRAM
for the
MicroMac
Performer
68kmla.org
·
16h
🧠
Memory Management
Best CPU 2026 – the top AMD
Ryzen
and Intel Core
processors
tested
club386.com
·
5h
🔢
SIMD
RISC-V
Mentorship
Taught Me the RISC-V
ISA
Is Far More Than a Reference Manual
riscv.org
·
2d
🔩
Assembly
Linux 7.0 Performance Events Prep For Intel
Xeon
Diamond
Rapids
phoronix.com
·
1d
📊
Performance Tools
Breaking the
Tractability
Barrier: A Generic Low-Level Solver for
NP-Hard
Instances (N=63) on Commodity 64-Bit Silicon
zenodo.org
·
5h
·
Discuss:
Hacker News
⚡
Zig
STMicroelectronics Stellar
P3E
quad-core Arm
Cortex-R52
+ automotive MCU features Neural-ART AI accelerator
cnx-software.com
·
5h
💻
Computer Hardware
Show HN:
SnesGPT
, micro-GPT ported to
ASM
on the Super Nintendo
github.com
·
1d
·
Discuss:
Hacker News
🔧
FPGA
General Old
Hardware
• Re:
Pushing
a 486 beyond 200MHz
vogons.org
·
18h
💻
Computer Hardware
FOSDEM
2026:
RISC-V
Hardware Is Here. What About Software? [video]
fosdem.org
·
2d
·
Discuss:
Hacker News
🔩
Assembly
Arch Linux Running Well On LoongArch -
Loongson
3B6000
Benchmarks
lxer.com
·
6h
📊
Performance Tools
Hardening the
OSv
Unikernel
with Efficient Address Randomization: Design and Performance Evaluation
arxiv.org
·
10h
🦀
Rust
Floating
bus
technical
guide
k1.spdns.de
·
1d
🔢
SIMD
AMD
openSIL
CPU Firmware Experiment Heading to Consumer
AM5
Boards
techpowerup.com
·
22h
🏗️
CPU Architecture
The RISC architecture frontier: Is
eBPF
ready for
ARM64
and RISC-V?
thenewstack.io
·
2d
🖥️
Operating Systems
C notes
dev.to
·
4h
·
Discuss:
DEV
🔩
Assembly
Discussion - Investigation of Single Thread CPU "
Thoughput/cycle
"
forums.anandtech.com
·
1d
🔢
SIMD
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