🖥️ Hardware Architecture - emschwartz · Scour

Building An AI Chip: Silicon Design And Advanced Packaging 🔬Chip Fabrication

semiengineering.com·1d

AHASD: Asynchronous Heterogeneous Architecture for LLM Adaptive Drafting Speculative Decoding on Mobile Devices 🧠LLM Inference

WhisperPipe: A Resource-Efficient Streaming Architecture for Real-Time Automatic Speech Recognition 🔬RaBitQ

Microarchitectural Co-Optimization for Sustained Throughput of RISC-V Multi-Lane Chaining Vector Processors ⚙️Mechanical Sympathy

NVLLM: A 3D NAND-Centric Architecture Enabling Edge on-Device LLM Inference 🏗️LLM Infrastructure

Exploiting pre-optimized kernels with polyhedral transformations for CGRA compilation 🧮Compute Optimization

SimdQuickHeap: The QuickHeap Reconsidered ⚡Vectorized Execution

Evaluating CUDA Tile for AI Workloads on Hopper and Blackwell GPUs ⚡Hardware Acceleration

arxiv.org·2d·Hacker News

Hardware-Software Co-Design for Event-Driven SNN Deployment on Low-Cost Neuromorphic FPGAs ⚡Hardware Acceleration

Stabilizers for Compiling Logical Circuits under Hardware Constraints 🧮SMT Solvers

Compilation and Execution of an Embeddable YOLO-NAS on the VTA ⚡Vectorized Execution

SparKV: Overhead-Aware KV Cache Loading for Efficient On-Device LLM Inference 🧠LLM Inference

Efficient Batch Search Algorithm for B+ Tree Index Structures with Level-Wise Traversal on FPGAs 🌳B+ Trees

A comprehensive evaluation of spatial co-execution on GPUs using MPS and MIG technologies ⚡Hardware Acceleration

AnalogMaster: Large Language Model-based Automated Analog IC Design Framework from Image to Layout 🏗️LLM Infrastructure

HGQ-LUT: Fast LUT-Aware Training and Efficient Architectures for DNN Inference 🔢BitNet Inference

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