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📏 Picolibc
Embedded C Library, Newlib Alternative, Small Footprint, RISC-V
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76509
posts in
421.1
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Hello Edge: Keyword
Spotting
on
Microcontrollers
paperium.net
·
23h
·
Discuss:
DEV
📱
Edge AI
Building Interactive C/C++ workflows in Jupyter through
Clang-REPL
[video]
fosdem.org
·
4h
·
Discuss:
Hacker News
🖥️
Ratatui
MicroBlaze
MCS Seven-Segment Counter on
Basys
3 FPGA
hackster.io
·
3h
🏗
Computer Architecture
Memory-Safe
Jule
language
emerges
as C/C++ alternative
thenewstack.io
·
3h
🍱
Nom
System-Level Isolation for
Mixed-Criticality
RISC-V
SoCs
: A "World" Reality Check
arxiv.org
·
1d
🎲
Hardware Branch Prediction
Chasing a Zig
AVR
Segfault
Down to LLVM
sourcery.zone
·
33m
·
Discuss:
r/Zig
⚙️
Zig
Advancing
the C language in today’s time means
improving
safety,
dev.to
·
7h
·
Discuss:
DEV
🏷️
Memory Tagging
feldera/feldera
: The
Feldera
Incremental
Computation Engine
github.com
·
9h
🔄
Salsa
Building a battle tested C
compiler
in a new language using
Codex
moonbitlang.com
·
1d
·
Discuss:
Hacker News
🔨
Compiler Design
Zinc
Language Design
ziggit.dev
·
10h
🦀
Rust
An Analysis of User-space
Idle
State Instructions on
x86
Processors
danglingpointers.substack.com
·
2d
·
Discuss:
Substack
⚙️
CPU Microarchitecture
Intel
ISPC
1.30 Released With
AMX
Support Added To The Standard Library
phoronix.com
·
2d
🔢
Intel AMX
Ubuntu on
RISC-V
might actually be good
thanks
to this chip
howtogeek.com
·
2d
⚡
RISC-V
C and C++
dependencies
, don't
dream
it, be it!
nibblestew.blogspot.com
·
2h
·
Discuss:
Hacker News
,
nibblestew.blogspot.com
🏗️
Build Systems
Declarative
,
Reproducible
Emacs
irreal.org
·
3h
🦀
Rust Macros
Concurrency
Deep Dive: Memory Models, Lock-Free, and
RCU
dev.to
·
5h
·
Discuss:
DEV
🚧
Memory Barriers
Modern
Trends
In
Floating-Point
semiengineering.com
·
2d
🛣️
Highway
Raspberry
Pico
: Programming with
PIO
State Machines
admantium.com
·
1d
⏱️
RTOS
Build a
Compiler
in Five Projects
kmicinski.com
·
9h
🔨
Compilers
The
Beacon
is
lit
blog.zarfhome.com
·
4h
⚡
LMAX Disruptor
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