🎨 Register Allocation - hello · Scour

CPU-less parallel execution of lambda calculus in digital logic

arxiv.org·21h

🔓Lock-Free Programming

One ISA, Infinite Use Cases: RISC-V and the Road to Workload-Specific Silicon

riscv.org·6h

GNU C Language Manual

gnu.org·7h

🔨Compiler Design

Union-Find Path Compression: A Visual Dry Run

dev.to·1d·

Discuss: DEV

📦Succinct Data Structures

Complexity of ArenaAllocator

ziggit.dev·1d

🏛️Region-Based Memory

FlashAttention 4: Faster, Memory-Efficient Attention for LLMs

digitalocean.com·14h

🔄Hardware Transactional Memory

Building Your Own Efficient uint128 in C++

solidean.com·1d·

Discuss: Lobsters, Hacker News, Hacker News, r/cpp

⚙️Cranelift Codegen

Memory layout matters: Reducing metric storage overhead by 4x in a Rust TSDB

baarse.substack.com·10h·

Discuss: r/rust

🏛️Region-Based Memory

SHADOW: Simultaneous Multi-Threading Architecture with Asymmetric Threads

danglingpointers.substack.com·1d·

Discuss: Substack

🧵Lightweight Threads

Streamlining CUB with a Single-Call API

developer.nvidia.com·4h

BPF Verifier State Pruning: Timeline

pchaigno.github.io·1d

A Novel Side-channel Attack That Utilizes Memory Re-orderings (U. of Washington, Duke, UCSC et al.)

semiengineering.com·7h

🔄Hardware Transactional Memory

PLA-Serve: A Prefill-Length-Aware LLM Serving System

arxiv.org·21h

Open-Source FPGA Implementation of an I3C Controller[v1]

preprints.org·1d

🔌FPGA Programming

Randomization in Typst

idraluna-archives.bearblog.dev·6h

🎲Deterministic Simulation

Scalable Adaptive Memory Compiler Optimization via Multi-Objective Evolutionary Algorithms

dev.to·23h·

Discuss: DEV

Extended parameter-shift rules with minimal derivative variance for parameterized quantum circuits

link.aps.org·18h

⚛️Quantum Computing

The Story on ISPC (Intel SPMD Program Compiler)

pharr.org·1d·

Discuss: Hacker News

Memory Addressing and Memory Mapped I/O | by Tom Herbert | Jan, 2026

medium.com·2d

Making a Language

thunderseethe.dev·3h

🔨Compiler Design

Loading more...