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Hardware Acceleration
⚡ Hardware Acceleration
GPU Computing, SIMD, Vector Instructions, Custom Silicon
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The
Hardware
That Makes AI Possible
🤖
AI
towardsdatascience.com
·
1d
1 day ago
Actions for The Hardware That Makes AI Possible
Exploring the Classic Xilinx XC5202-6PQ100I
FPGA
💾
Computer Architecture
hackster.io
·
14h
14 hours ago
Actions for Exploring the Classic Xilinx XC5202-6PQ100I FPGA
FlexNPU: Transparent
NPU
Virtualization for Dynamic LLM Prefill-Decode
Co-location
⚡
HFT
Content type:
Academic
arxiv.org
·
6d
6 days ago
Actions for FlexNPU: Transparent NPU Virtualization for Dynamic LLM Prefill-Decode Co-location
I stopped using most of Rust’s advanced features for my ML library
🤖
AI
Content type:
Code
github.com
·
2d
2 days ago
·
r/rust
Actions for I stopped using most of Rust’s advanced features for my ML library
Founding Engineer -
FPGA
, RTL, &
ASIC
Architect at Zettascale
💾
Computer Architecture
ycombinator.com
·
6d
6 days ago
·
Hacker News
Actions for Founding Engineer - FPGA, RTL, & ASIC Architect at Zettascale
Ultrafast machine learning on
FPGAs
via Kolmogorov-Arnold Networks
🤖
AI
aarushgupta.io
·
1d
1 day ago
·
Lobsters
,
Hacker News
Actions for Ultrafast machine learning on FPGAs via Kolmogorov-Arnold Networks
Why my
SIMD
code was silently running as scalar, and what debugging it taught me about production environment assumptions
🎮
Game Engines
Content type:
Blog
coloneltoad.substack.com
·
6d
6 days ago
·
Substack
Actions for Why my SIMD code was silently running as scalar, and what debugging it taught me about production environment assumptions
Latency-Aware, High-Throughput Homomorphic AES Evaluation with CKKS
🔐
Cryptography
eprint.iacr.org
·
2d
2 days ago
Actions for Latency-Aware, High-Throughput Homomorphic AES Evaluation with CKKS
The Edge LLM Offload Story
🤖
AI
semiengineering.com
·
6d
6 days ago
Actions for The Edge LLM Offload Story
1-bit and 1.58 bit LLM Benchmarking on Jetson Orin Nano Super | Bonsai LM
💬
LLMs
smolhub.com
·
2d
2 days ago
·
r/LocalLLaMA
Actions for 1-bit and 1.58 bit LLM Benchmarking on Jetson Orin Nano Super | Bonsai LM
DeepSeekV4 1.6T Day 0 to Day 43 Performance Over Time - Huawei, GB300 NVL72, MI355X, B200
💬
LLMs
Content type:
News
newsletter.semianalysis.com
·
1d
1 day ago
·
Hacker News
Actions for DeepSeekV4 1.6T Day 0 to Day 43 Performance Over Time - Huawei, GB300 NVL72, MI355X, B200
Towards Autonomous
Accelerator
Design:
FPGA
Accelerator
Generation with SECDA
💾
Computer Architecture
Content type:
Academic
arxiv.org
·
16h
16 hours ago
Actions for Towards Autonomous Accelerator Design: FPGA Accelerator Generation with SECDA
DiffusionGemma: 4x Faster Text Generation
💬
LLMs
Content type:
News
Content type:
Blog
blog.google
·
4h
4 hours ago
·
Hacker News
,
r/LocalLLaMA
,
r/singularity
Actions for DiffusionGemma: 4x Faster Text Generation
Niobium
Opens
Developer Partner Program for The Fog, the First IaaS Purpose-Built for Fully Homomorphic Encryption
🔐
Cryptography
sdtimes.com
·
5d
5 days ago
Actions for Niobium Opens Developer Partner Program for The Fog, the First IaaS Purpose-Built for Fully Homomorphic Encryption
Why Compiler Engineers Rarely Use Strassen's Algorithm for Fast Matrix Multiplications
🧮
Complexity Theory
Content type:
News
Content type:
Blog
leetarxiv.substack.com
·
2d
2 days ago
·
Substack
,
r/programming
Actions for Why Compiler Engineers Rarely Use Strassen's Algorithm for Fast Matrix Multiplications
The copy_if Speedup That Wasn't About copy_if, Or AVX-512
🏗️
LLVM
hftuniversity.com
·
6d
6 days ago
·
Substack
Actions for The copy_if Speedup That Wasn't About copy_if, Or AVX-512
Unpacking AI: The
Hardware
Behind AI
🤖
AI
Content type:
News
pathtostaff.com
·
4d
4 days ago
·
Hacker News
Actions for Unpacking AI: The Hardware Behind AI
Build settings in binary crates via cargo install and crates.io
⚙️
MLOps
nnethercote.github.io
·
1d
1 day ago
·
r/rust
Actions for Build settings in binary crates via cargo install and crates.io
Arithmetic Packing on Wide Integer Datapaths in DSP Primitives of Modern
FPGA
Devices
💾
Computer Architecture
Content type:
Academic
arxiv.org
·
16h
16 hours ago
Actions for Arithmetic Packing on Wide Integer Datapaths in DSP Primitives of Modern FPGA Devices
SWIFT: Shallow and
SIMD-Aware
CKKS Functional Bootstrapping for Low-Latency
⚡
Speculative Decoding
eprint.iacr.org
·
6d
6 days ago
Actions for SWIFT: Shallow and SIMD-Aware CKKS Functional Bootstrapping for Low-Latency
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