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Computer Architecture
💻 Computer Architecture
CPU design, microarchitecture, pipeline, ISA, processor design
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RISC-V
Targets Data Centers, Edge AI, Space
🐧
Operating Systems
Content type:
News
eetimes.com
·
2d
2 days ago
Actions for RISC-V Targets Data Centers, Edge AI, Space
(
PR
) NextSilicon to Productize Arbel
RISC-V
Core Into 64-Core Enterprise Processor for AI and HPC
🖥️
HPC
techpowerup.com
·
3d
3 days ago
Actions for (PR) NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC
Red Hat Releases Second Developer Preview Of RHEL 10 For
RISC-V
🐧
Operating Systems
phoronix.com
·
1d
1 day ago
Actions for Red Hat Releases Second Developer Preview Of RHEL 10 For RISC-V
Retro New? OS/Languages?
🐧
Operating Systems
Content type:
Video
retrocomputingforum.com
·
16h
16 hours ago
Actions for Retro New? OS/Languages?
"
RISC-V
Is Now"
🐧
Operating Systems
Content type:
Video
youtube.com
·
4d
4 days ago
·
Hacker News
Actions for "RISC-V Is Now"
Linux 7.2 To Enable ESWIN SoC Support By Default For
RISC-V
Kernel Builds
🐧
Operating Systems
lxer.com
·
2d
2 days ago
Actions for Linux 7.2 To Enable ESWIN SoC Support By Default For RISC-V Kernel Builds
The Tick-Tock AI Development Cycle.
📐
SIMD
wilsoniumite.com
·
3d
3 days ago
Actions for The Tick-Tock AI Development Cycle.
Openchip taps Baya Systems data-movement platform for
RISC-V
systems
🖥️
HPC
siliconangle.com
·
2d
2 days ago
Actions for Openchip taps Baya Systems data-movement platform for RISC-V systems
SupraSNN: Exploiting Synapse-Level Parallelism in Spiking Neural Network Accelerators through
Co-Optimized
Mapping and Scheduling
🔲
FPGA
Content type:
Academic
arxiv.org
·
2d
2 days ago
Actions for SupraSNN: Exploiting Synapse-Level Parallelism in Spiking Neural Network Accelerators through Co-Optimized Mapping and Scheduling
SpacemiT shows off usably quick
RISC-V
mini desktop
📐
SIMD
Content type:
News
theregister.com
·
3d
3 days ago
·
r/hardware
Actions for SpacemiT shows off usably quick RISC-V mini desktop
coherentforge/CambiOS: Zero-trust, capability-based Rust microkernel targeting formal verification.
Tri-arch
(x86_64 / AArch64 /
RISC-V
). Sovereign and generative: no telemetry, user owns keys and data. Early-stage — see STATUS.md. Inspired by seL4, Hubris, and Redox.
🐧
Operating Systems
Content type:
Code
github.com
·
2d
2 days ago
·
Hacker News
Actions for coherentforge/CambiOS: Zero-trust, capability-based Rust microkernel targeting formal verification. Tri-arch (x86_64 / AArch64 / RISC-V). Sovereign and generative: no telemetry, user owns keys and data. Early-stage — see STATUS.md. Inspired by seL4, Hubris, and Redox.
RISC-V
edge box packs dual GbE, CAN, and 4G/5G support
🎮
GPU Computing
linuxgizmos.com
·
6d
6 days ago
Actions for RISC-V edge box packs dual GbE, CAN, and 4G/5G support
2 to 4 cents Fortior FU75xx dual-core motor control MCU family combines 32-bit
RISC-V
core with 2nd-gen Motor Engine (ME2) core - CNX Software
🔲
FPGA
Content type:
News
cnx-software.com
·
1d
1 day ago
Actions for 2 to 4 cents Fortior FU75xx dual-core motor control MCU family combines 32-bit RISC-V core with 2nd-gen Motor Engine (ME2) core - CNX Software
Fedora 44
RISC-V
Images Released, Including New "Omni" Kernel For Broader
RISC-V
Hardware Support
🐧
Operating Systems
lemmy.ml
·
3d
3 days ago
Actions for Fedora 44 RISC-V Images Released, Including New "Omni" Kernel For Broader RISC-V Hardware Support
How To Start Building Edge-Native AI
📐
SIMD
semiengineering.com
·
2d
2 days ago
Actions for How To Start Building Edge-Native AI
Vortex expands open
RISC-V
graphics
🎮
GPU Computing
jonpeddie.com
·
3d
3 days ago
Actions for Vortex expands open RISC-V graphics
Operation Costs in
CPU
Clock Cycles (2016)
📐
SIMD
Content type:
Blog
6it.dev
·
15h
15 hours ago
·
Hacker News
Actions for Operation Costs in CPU Clock Cycles (2016)
Open Source Hardware Certifications for May 2026
🔲
FPGA
makezine.com
·
5d
5 days ago
Actions for Open Source Hardware Certifications for May 2026
Difference between revisions of "ELC 2026 Presentations"
🐧
Operating Systems
elinux.org
·
2d
2 days ago
Actions for Difference between revisions of "ELC 2026 Presentations"
The Boot Chain of a
RISC-V
Board: From Silicon to Ubuntu 26.04
🐧
Operating Systems
Content type:
Blog
blog.ludovic.dev
·
6d
6 days ago
·
Hacker News
,
Hacker News
Actions for The Boot Chain of a RISC-V Board: From Silicon to Ubuntu 26.04
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