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AutoFlows++: Hierarchical Message Flow Mining for System on Chip Designs  🎯Performance Forensics
arxiv.org·5d
High-Fidelity KV Cache Summarization Using Entropy and Low-Rank Reconstruction  📼Tape Combinators
jchandra.com·6d·Hacker News, r/LocalLLaMA
SONIC: Concurrent Oblivious RAM & Data Structures for Low-Latency and High-Throughput  ⚡Hardware Transactional Memory
usenix.org·5d
Scalable AI Inference: Performance Analysis and Optimization of AI Model Serving  💻Local LLMs
arxiv.org·2d
A Novel Low-Power Cache Architecture Based on 6-Transistor SRAM Cells  🖥️Hardware Architecture
arxiv.org·2d
A Complementary Visualisation Suite for Empirical Performance Analysis: Tempographs, Histograms, Ridgeline Plots, Stacked Bar Charts, and Combination Charts Applied to Beethoven's Piano and Cello Sonatas  🎼Computational Musicology
arxiv.org·3d
Toward designing workload-aware Surface Code Architectures  🖥️Hardware Architecture
arxiv.org·2d
Fault-Tolerant Quantum Computing with Trapped Ions: The Walking Cat Architecture  ⚛️Quantum Error Correction
arxiv.org·3d
Photonic AI: A Hybrid Diffractive Holographic Neural System for Passive Optical Real-Time Image Classification  🌈Holographic Archives
arxiv.org·5d
Design Space Exploration for ReRAM-based Architectures to Address Scaling Non-idealities  🧩RISC-V
arxiv.org·2d
How Much Cache Does Reasoning Need? Depth-Cache Tradeoffs in KV-Compressed Transformers  📼Tape Combinators
arxiv.org·4d
SAW-INT4: System-Aware 4-Bit KV-Cache Quantization for Real-World LLM Serving  🖥️Hardware Architecture
arxiv.org·3d·Hacker News
Different Perspectives of Memory System Simulation  🔩Systems Programming
arxiv.org·4d·Hacker News
Homogeneous Network Caching is Fixed-Parameter Tractable Parameterized by the Number of Caches  ⚡Cache Coherence
arxiv.org·4d
MoE-nD: Per-Layer Mixture-of-Experts Routing for Multi-Axis KV Cache Compression  ⚡CPU Microarchitecture
arxiv.org·4d
Sequential KV Cache Compression via Probabilistic Language Tries: Beyond the Per-Vector Shannon Limit  🌊Streaming Compression
arxiv.org·5d·Hacker News
Fleet: Hierarchical Task-based Abstraction for Megakernels on Multi-Die GPUs  💨Cache Analysis
arxiv.org·5d
PoSME: Proof of Sequential Memory Execution via Latency-Bound Pointer Chasing with Causal Hash Binding  🦀Rust Verification
arxiv.org·5d
AccelCIM: Systematic Dataflow Exploration for SRAM Compute-in-Memory Accelerator  ⚡CPU Microarchitecture
arxiv.org·4d
Low-Stack HAETAE for Memory-Constrained Microcontrollers  ⚡CPU Microarchitecture
arxiv.org·5d

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