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A Comparative Analysis of ARM and x86-64 Laptop-Class Processors: Architecture, Assembly-Level Performance, and Energy Efficiency  🦾ARM Assembly
arxiv.org·3d
Your CPU Has More Registers Than You'd Think  ⚡CPU Microarchitecture
fp32.org·2d·Lobsters
Building a RISC-V CPU Core (LFD111x) | Linux Foundation Education  🧩RISC-V
training.linuxfoundation.org·5d·Hacker News
Microcontrollers for Machine Learning  🔌Microcontrollers
embedded.com·4d
Toward designing workload-aware Surface Code Architectures  ⚡CPU Microarchitecture
arxiv.org·2d
Optimizing Branch Predictor for Graph Applications  🔗Topological Sorting
arxiv.org·3d
A Novel Low-Power Cache Architecture Based on 6-Transistor SRAM Cells  ⚡Cache Theory
arxiv.org·2d
Design Space Exploration for ReRAM-based Architectures to Address Scaling Non-idealities  🧩RISC-V
arxiv.org·2d
Proxics: an efficient programming model for far memory accelerators  ⚡Hardware Transactional Memory
arxiv.org·4d
Low-Stack HAETAE for Memory-Constrained Microcontrollers  ⚡CPU Microarchitecture
arxiv.org·5d
SAW-INT4: System-Aware 4-Bit KV-Cache Quantization for Real-World LLM Serving  ⚡LZ4 Streaming
arxiv.org·3d·Hacker News
Idle is the New Sleep: Configuration-Aware Alternative to Powering Off FPGA-Based DL Accelerators During Inactivity  🔧FPGA Preservation
arxiv.org·3d
Silicon Aware Neural Networks  📊Quantization
arxiv.org·3d
CIMple: Standard-cell SRAM-based CIM with LUT-based split softmax for attention acceleration  ⚡Hardware Transactional Memory
arxiv.org·5d
MoE-nD: Per-Layer Mixture-of-Experts Routing for Multi-Axis KV Cache Compression  ⚡CPU Microarchitecture
arxiv.org·4d
Energy Efficient LSTM Accelerators for Embedded FPGAs through Parameterised Architecture Design  ⚡Compression Hardware
arxiv.org·3d
Different Perspectives of Memory System Simulation  🔩Systems Programming
arxiv.org·4d·Hacker News
MemExplorer: Navigating the Heterogeneous Memory Design Space for Agentic Inference NPUs  ⚡Hardware Transactional Memory
arxiv.org·5d
AccelCIM: Systematic Dataflow Exploration for SRAM Compute-in-Memory Accelerator  ⚡CPU Microarchitecture
arxiv.org·4d
Fleet: Hierarchical Task-based Abstraction for Megakernels on Multi-Die GPUs  💨Cache Analysis
arxiv.org·5d

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