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🖥️ Hardware Architecture

CPU Design, Cache Optimization, Instruction Sets, Microarchitecture

Evaluation of Hashing Algorithms Ascon, SHA256, SHA512 and BLAKE3 on a Cortex M7
aa55.dev·19h·
Discuss: Hacker News
🦾ARM Cortex-M
From Logic to Linear Algebra: How AI is Rewiring the Computer
dev.to·20h·
Discuss: DEV
⚡Homebrew CPUs
How I Approach Performance Investigations – By Rico Mariani
ricomariani.medium.com·15h·
Discuss: Hacker News
🎯Performance Forensics
Show HN: Novel GPT-2 sampling and memory architecture
github.com·2d·
Discuss: Hacker News
💎Information Crystallography
Kioxia demonstrates ultra fast SSD that uses innovative tech to deliver a staggering 64GBps on PCIe Gen6 - and no, it's not coming to a PC near you anytime soon
techradar.com·18h
🖥️Terminal Renaissance
Fast and Accurate RFIC Performance Prediction via Pin Level Graph Neural Networks and Probabilistic Flow
arxiv.org·8h
🧠Machine Learning
RTL generation for custom CPU Mrav
popovicu.com·1d
⚙️Modern Assembly
Breathing New Life into an Old HP ProLiant N40L
reddit.com·1d·
Discuss: r/homelab
🇳🇱Dutch Computing
Explanation of the Linux-Kernel Memory Consistency Model
raw.githubusercontent.com·1d·
Discuss: Lobsters, Hacker News
⚡Cache Coherence
Memory optimizations to reduce CPU costs
ayende.com·1h·
Discuss: Hacker News
📝Text Compression
Thin mini-ITX industrial motherboard features Intel Core Ultra 5 225H or Ultra 7 255H Arrow Lake-H SoC
cnx-software.com·8h
🖥️Modern Terminals
From Logic to Linear Algebra: How AI Is Rewiring the Computer
journal.hexmos.com·20h·
Discuss: Hacker News, r/programming
🇷🇺Russian Computing
This is an excellent patch review by an expert, i.e., Thomas :) And it should be like this. Oh, a few days back I saw one from Greg too, a similar kind.... in t...
lore.kernel.org·5h·
Discuss: r/linux
🔌Operating system internals
Physics-inspired computer architecture solves complex optimization problems
phys.org·2d
⚛️Information Physics
TaMaRa: Towards a Triple Modular Redundancy Pass for Yosys
blog.yosyshq.com·1d·
Discuss: Lobsters, Hacker News
🔍FPGA Verification
XCENA MX1 RISC-V Computational Memory in CXL 3.0
servethehome.com·20h
⚡Hardware Transactional Memory
google/highway
github.com·1d
📊RISC-V Vectors
Sets & Heaps in Haskell and Rust
mmhaskell.com·3h
🔒Type Safety
ColecoVision: The Shooting Gallery Platform Layer
bumbershootsoft.wordpress.com·1d
🎮Gameboy Emulation
The 32 Bit 6502 You Never Had
hackaday.com·1d
🍎Apple II Heritage
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