The Next Computing Revolution: Bringing Processing Inside Memory
computer.org·15h·
Discuss: Hacker News
Hardware Transactional Memory
Rigorous Evaluation of Microarchitectural Side-Channels with Statistical Model Checking
arxiv.org·1d
🔧Hardware Verification
The Chip That Spoke Lisp
jxself.org·1h
🤖Lisp Machines
Beating the L1 cache with value speculation (2021)
mazzo.li·21h·
CPU Microarchitecture
Hardware Stockholm Syndrome
programmingsimplicity.substack.com·12h·
Discuss: Substack
🔩Systems Programming
A Primer on Memory Consistency and Cache Coherence, Second Edition
link.springer.com·1d·
Discuss: r/programming
Cache Coherence
The Role of AI in Next-Gen Chip Design
dev.to·1d·
Discuss: DEV
🔧Hardware Verification
LLM Optimization Notes: Memory, Compute and Inference Techniques
gaurigupta19.github.io·21h·
Discuss: Hacker News
💻Local LLMs
CPU Cache-Friendly Data Structures in Go: 10x Speed with Same Algorithm
skoredin.pro·1d·
Discuss: Hacker News
💨Cache Optimization
We built a CUDA emulator that profiles GPU code with zero hardware
rightnowai.co·12h·
Discuss: Hacker News
🎯Emulator Accuracy
1GHz Renesas RA8T2 Cortex-M85 MCUs feature MRAM and EtherCAT for industrial motor control
cnx-software.com·1d
🦾ARM Cortex-M
Homelab Planning
reddit.com·12h·
Discuss: r/homelab
🏠HomeLab
🔥 How to Make the Best IoT Project using PIC16F877A
hackster.io·32m
🔌Single Board PC
Why We Need SIMD
parallelprogrammer.substack.com·1d·
Discuss: Substack
📊RISC-V Vectors
Why We Created Turso, a Rust-Based Rewrite of SQLite
thenewstack.io·21h
💾SQLite
Latency vs. Accuracy for LLM Apps — How to Choose and How a Memory Layer Lets You Win Both
dev.to·1h·
Discuss: DEV
Performance Mythology
Evading the Watchful Eye: A Red Teamer’s Guide to EDR Bypass Techniques
medium.com·1d
🔐Cryptographic Archaeology
Software for Hardware – Digitizing the Physical World
generalcatalyst.com·1h·
Discuss: Hacker News
🔗Supply Chain
Dragon Hatchling: Neural Network That Thinks Like a Brain (and Runs on Your GPU)
medium.com·1h·
Discuss: Hacker News
🔲Cellular Automata