Circuit Design

Logic Synthesis, Hardware Description Languages, Digital Electronics, Circuit Verification

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Scoured 26 posts in 19.9 ms

StepPRM-RTL: Stepwise Process-Reward Guided LLM Fine-Tuning for Enhanced RTL Synthesis

 ⚙️Logic Synthesis  Content type: Academic
arxiv.org·

MMO-CHIP: From Microscope to Verilog in an hour

 🔬Binary Analysis  Content type: Video
media.ccc.de··Lobsters

geohot/fromthetransistor: From the Transistor to the Web Browser, a rough outline for a 12 week course

 ⚙️Logic Synthesis  Content type: Code
github.com··Hacker News

AWS can now mathematically prove your VMs are isolated

 💻Operating System, OS
thenewstack.io·

Founding Engineer - FPGA, RTL, & ASIC Architect at Zettascale

 ⚙️Logic Synthesis

Exploring the Classic Xilinx XC5202-6PQ100I FPGA

 ⚙️Logic Synthesis
hackster.io·

Ask HN: What has been the fate of code review?

 💻Programming languages  Content type: Discussion

From PAL to Verilog: Writing the A4092 Logic from Scratch (amiga.technology)

 ⚙️Logic Synthesis  Content type: Blog
amiga.technology·

Now available: Amazon EC2 M9g and M9gd instances powered by new AWS Graviton5 processors

 💻Programming languages  Content type: Blog
aws.amazon.com··Hacker News

The Orchard Bug and the Unfolding Cybersecurity Reckoning

 💻Programming languages  Content type: News  Content type: Blog

RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models

 🔧Hardware Verification  Content type: Academic
arxiv.org·

ROSUM-MCTS: Monte Carlo Tree Search-Inspired HDL Code Summarization with Structural Rewards

 ⚙️Logic Synthesis  Content type: Academic
arxiv.org·

List StarWhisper on Hacker News (Show HN)

 🌿git  Content type: Discussion

Programming Domain-Specific FPGA Hardblocks from HLS: An RTL Blackbox Approach

 ⚙️Logic Synthesis  Content type: Academic
arxiv.org·

rochus-keller/EXPRESS: A parser and code model for the ISO 10303 EXPRESS language with a lot more interesting stuff to come

 💻Programming languages  Content type: Code
github.com··Hacker News

Syntax-driven Incremental Program Verification of Matching Logic Properties

 💻Programming languages  Content type: Academic
arxiv.org·

Formal verification of the S-two AIR

 💻Programming languages  Content type: Academic
arxiv.org·

Abduction Prover in Isabelle/HOL

 👑Isabelle/HOL  Content type: Academic
arxiv.org·

GCD: Garbled, Corrected, Demonstrandum -- Fixing and Proving Go's Extended GCD Implementation

 💻Programming languages  Content type: Academic
arxiv.org·

VASO: Formally Verifiable Self-Evolving Skills for Physical AI Agents

 🌐NetworkProtocols  Content type: Academic
arxiv.org·

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