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Artificial intelligence (AI) is transforming how the world builds and uses computer chips. From massive data centers to devices at the edge of the network, AI requires chips continuing to get faster, smaller and more energy-efficient.

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For decades, Moore’s Law, which accurately predicted that the number of transistors on a computer chip would double around every two years, kept the industry moving forward.

Unfortunately, conventional scaling approaches through planar complementary metal-oxide-semiconductor (CMOS) devices, or FinFETs, which extended Moore’s Law, have reached their limits. The industry is now facing a critical challenge: trying to keep advancing chip technology when the old rule of thumb no longer applies.

The industry’s answer is gate-all-around (GAA). This design wraps the gate material completely around all sides, including the control part of the chip, known as the gate, that carries the electric current.

This gives engineers more precise control over how electricity flows through the chip, enabling GAA devices to perform better even as the industry carries onto the next node. This also allows more power without taking up more area.

The new bottlenecks

But GAA isn’t perfect. While it solves challenges via lower power consumption and more efficient use of space, it moves the bottleneck to other areas.

Specifically, older chips encounter resistance — anything that slows down electricity — from inside the channel. Most of the resistance comes from the contact points and areas where the current enters and exits.

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To fix this, engineers have added materials called dopants to help electricity flow better. But during this doping process, the dopants can inadvertently spread to nearby places on the chip that should be undoped.

When this happens, it can not only affect performance but create additional issues in the chip such as increased leakage, change the threshold voltage or introduce variability.

Another challenge stems from the manufacturing process, specifically when silicon-germanium (SiGe) layers are removed to shape parts of the chip.

This can leave behind rough surfaces and interfere with how smoothly electricity flows through the devices. Later, when metal contacts are added on top, this creates further resistance at the point where the metal and silicon meet.

In short, GAA may address electrostatics challenges, but it also introduces new ones. This is where advanced materials come into play.

Atomic-scale materials, big fixes

To tackle these new challenges, chipmakers are turning to advanced materials and working at the atomic level to help realize the full potential of GAA.

Here’s how these new materials help:

• Blocking unwanted dopant diffusion: Inserting an advanced barrier between heavily doped and undoped areas can prevent dopants from seeping into other areas of the chip. This containment is essential for boosting performance.
• Smoothing surfaces: Rough surfaces at the atomic level can scatter electrons and slow them down. Advanced materials engineering can smooth out surfaces that may become uneven during the removal of sacrificial SiGe layers, reducing this scattering. This can boost carrier mobility under normal operating conditions, resulting in more current, faster switching and better performance, all without requiring more power.
• Boosting power without compromising size: Advanced materials allow engineers to pack thinner performance structures into the same space. This change can boost current per footprint by about 10% without increasing chip size.
• Reducing contact resistance: As device dimensions get smaller, the electrical contact resistance at the point where metal connects to silicon becomes a major limiting factor. By modifying the materials at these junctions, engineers can significantly lower resistance and unlock greater efficiency.

Looking ahead

The explosive growth of AI is driving a fundamental shift in how the industry thinks about computing efficiency. Engineers now face an increasingly complex trade-off between power, performance, area and cost (PPAC).

In the past, the industry has relied on incremental improvements to stay on track, but with the scale and intensity of AI pushing existing architectures to their limits, these small gains are no longer sufficient.

To unlock the next wave of progress, the industry needs a more transformational shift, one that resets the foundation and enables further improvements to continue delivering impact.

The next node, also referred to as the angstrom era, will accelerate innovations in advanced materials beyond what’s possible today to deliver advancements across the PPAC equation. GAA is just the beginning.

To keep shrinking and improving chips for massive AI systems, engineers are exploring new ways to deliver more with less. These breakthroughs in advanced materials are empowering the industry to achieve more performance with less space and energy, driving smarter and more sustainable computing across the board.

Beyond GAA, the industry is already doing work on a new structure called a CFET, or complementary FET, which may take us a few more generations before we start looking at 3D structures like stacked CFETs to keep Moore’s Law progressing.

One thing is certain is that new advanced materials will be required at each step of the way to unleash the performance that these new transistor structures are designed to enable.

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