Today, AMD introduced the AMD Kintex UltraScale+ Gen 2 FPGA family, a major step forward for designers who rely on mid-range FPGAs to power performance-critical systems. Building on the proven Kintex FPGA portfolio legacy, this new family modernizes memory, I/O, and security to meet the growing demands of imaging, test and measurement, industrial automation, and professional 4K/8K media workflows.

Built for Demanding, Data-Intensive Workloads AMD Kintex UltraScale+ Gen 2 FPGAs are engineered to meet the increasingly complex system requirements across broadcast, test, industrial, and medical markets.

• Dense 4K/8K media workflows: High-speed transceivers and PCIe Gen 4 support 4K AV-over-IP, multi-stream capture, and frame-accurate transport for professional broadcast and remote production.
• High-throughput test and measurement: Increased memory bandwidth helps accelerate pattern generation, fail capture, and timing-critical workloads across semiconductor test and inspection systems.
• Advanced imaging and real-time control: Scalable sensor connectivity improves diagnostic clarity and responsiveness in machine vision, industrial automation, medical imaging, and robotic systems.
• Migration path with Spartan UltraScale+ FPGAs: Start now with the XCSU200P in the SBVF900 package and then migrate to Kintex UltraScale+ Gen 2 FPGAs in Q4 2026.

Integrated LPDDR4X/5/5X controllers with high DDR bandwidth and deterministic performance allow designers to build systems that keep pace with ever-growing data rates, while maintaining tight control over latency and power efficiency.

A New Standard for Mid-Range Performance Kintex UltraScale+ Gen 2 devices extend AMD leadership in mid-range FPGAs by delivering up to 5X increase in memory bandwidth compared to the prior generation, along with up to 2X higher channel density per PCIe interface. These advances translate directly into higher throughput, lower latency, and more responsive systems, without pushing designers into higher-cost device classes.

Kintex UltraScale+ Gen 2 FPGAs modernize mid-range FPGA capabilities to address growing bandwidth, timing precision, and connectivity demands across key markets. Compared to competing platforms, the family delivers up to 80% higher embedded RAM and 2X DSP density and substantially higher LPDDR memory bandwidth, while maintaining the security and lifecycle support critical, regulated, and long-lived systems.

With scalable high-speed I/O, modernized memory subsystems, and deterministic fabric behavior, Kintex UltraScale+ Gen 2 FPGAs enable faster on-device processing and adaptable pipelines that can respond in real time while scaling to future throughput requirements.

Enhanced Security and Longevity Many Kintex-based systems operate in environments where long product lifecycles, certification stability, and trusted operation are critical requirements. Kintex UltraScale+ Gen 2 FPGAs reinforce our long-standing commitment to these markets by integrating advanced security capabilities directly into the device.

Features such as authenticated device operation, bitstream encryption, anti-cloning protections, secure key management, and CNSA 2.0-grade cryptography help safeguard intellectual property and protect systems operating in distributed, connected, and regulated environments.

Beyond security, the Kintex UltraScale+ Gen 2 FPGA is designed for longevity. With planned availability through at least 2045, the family provides the supply assurance that industrial, medical, broadcast, and test equipment manufacturers rely on to support multi-decade deployments while helping minimize redesign cycles and maintain regulatory certifications over time.

Equally important is development continuity. By building on proven AMD Vivado and Vitis tools and a mature portfolio of AMD video, Ethernet, and connectivity IP, Kintex UltraScale+ Gen 2 devices offer a stable, predictable path forward.

Availability and Getting Started Simulation support for the Vivado and Vitis tools are scheduled for Q3 2026, giving development teams the early access needed to begin architecture exploration and design work.

Pre-production XC2KU050P FPGA silicon will follow with sampling in Q4 2026, enabling early hardware validation and performance characterization, with production anticipated in the first half of 2027. A Kintex UltraScale+ Gen 2 evaluation kit, based on the XC2KU050P FPGA, will start sampling in Q4 2026.

The existing Spartan UltraScale+ SCU200 Evaluation Kit, based on the migration-capable XCSU200P device, is available today for designers who want early hands-on experience with PCIe Gen 4, hard memory controllers, and advanced security features.