Skip to main content
Scour
Browse
Getting Started
Login
Sign Up
You are offline. Trying to reconnect...
Copied to clipboard
Unable to share or copy to clipboard
CPU Architecture
💻 CPU Architecture
microarchitecture, cache, pipeline, SIMD, branch prediction
Filter Results
Timeframe
Fresh
Past Hour
Today
This Week
This Month
Feeds to Scour
Subscribed
All
Scoured
218
posts in
8.4
ms
RISC-V
Targets Data Centers, Edge AI, Space
⚡
Performance
Content type:
News
eetimes.com
·
1d
1 day ago
Actions for RISC-V Targets Data Centers, Edge AI, Space
How much do amd64
microarchitecture
levels help in Go?
🛠️
Compilers
Content type:
Blog
lemire.me
·
6d
6 days ago
·
Lobsters
,
Hacker News
,
r/golang
Actions for How much do amd64 microarchitecture levels help in Go?
AVX-512
Optimization For Linux RAID Showing Up To 41% Improvement On AMD Ryzen 9 9950X
⚙️
Systems Engineering
phoronix.com
·
11h
11 hours ago
Actions for AVX-512 Optimization For Linux RAID Showing Up To 41% Improvement On AMD Ryzen 9 9950X
Release v0.15.0-alpha.3 · UniClipboard/UniClipboard
🛠️
Compilers
Content type:
Code
github.com
·
17h
17 hours ago
Actions for Release v0.15.0-alpha.3 · UniClipboard/UniClipboard
Linux 7.2 To Enable ESWIN SoC Support By Default For
RISC-V
Kernel Builds
⚙️
Systems Engineering
lxer.com
·
1d
1 day ago
Actions for Linux 7.2 To Enable ESWIN SoC Support By Default For RISC-V Kernel Builds
"
RISC-V
Is Now"
⚙️
Systems Engineering
Content type:
Video
youtube.com
·
3d
3 days ago
·
Hacker News
Actions for "RISC-V Is Now"
(
PR
) NextSilicon to Productize Arbel
RISC-V
Core Into 64-Core Enterprise Processor for AI and HPC
📦
Big Data
techpowerup.com
·
2d
2 days ago
Actions for (PR) NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC
2 to 4 cents Fortior FU75xx dual-core motor control MCU family combines 32-bit
RISC-V
core with 2nd-gen Motor Engine (ME2) core - CNX Software
🎯
Low Latency
Content type:
News
cnx-software.com
·
14h
14 hours ago
Actions for 2 to 4 cents Fortior FU75xx dual-core motor control MCU family combines 32-bit RISC-V core with 2nd-gen Motor Engine (ME2) core - CNX Software
SpacemiT shows off usably quick
RISC-V
mini desktop
🎯
Low Latency
Content type:
News
theregister.com
·
2d
2 days ago
·
r/hardware
Actions for SpacemiT shows off usably quick RISC-V mini desktop
SupraSNN: Exploiting Synapse-Level Parallelism in Spiking Neural Network Accelerators through Co-Optimized Mapping and Scheduling
🎯
Low Latency
Content type:
Academic
arxiv.org
·
17h
17 hours ago
Actions for SupraSNN: Exploiting Synapse-Level Parallelism in Spiking Neural Network Accelerators through Co-Optimized Mapping and Scheduling
RISC-V
edge box packs dual GbE, CAN, and 4G/5G support
🎯
Low Latency
linuxgizmos.com
·
4d
4 days ago
Actions for RISC-V edge box packs dual GbE, CAN, and 4G/5G support
Fedora 44
RISC-V
Images Released, Including New "Omni" Kernel For Broader
RISC-V
Hardware Support
⚙️
Systems Engineering
lemmy.ml
·
2d
2 days ago
Actions for Fedora 44 RISC-V Images Released, Including New "Omni" Kernel For Broader RISC-V Hardware Support
The Tick-Tock AI Development Cycle.
💥
Chaos Engineering
wilsoniumite.com
·
2d
2 days ago
Actions for The Tick-Tock AI Development Cycle.
Open Source Hardware Certifications for May 2026
💥
Chaos Engineering
makezine.com
·
4d
4 days ago
Actions for Open Source Hardware Certifications for May 2026
When JavaScript Isn't Fast Enough
🖥️
Bytecode VMs
napi.rs
·
5h
5 hours ago
·
DEV
Actions for When JavaScript Isn't Fast Enough
Correct workflow for stage3 and stage 4 building, testing and debugging
🛠️
Compilers
ziggit.dev
·
1d
1 day ago
Actions for Correct workflow for stage3 and stage 4 building, testing and debugging
Openchip taps Baya Systems data-movement platform for
RISC-V
systems
📦
Big Data
siliconangle.com
·
1d
1 day ago
Actions for Openchip taps Baya Systems data-movement platform for RISC-V systems
The Boot Chain of a
RISC-V
Board: From Silicon to Ubuntu 26.04
⚙️
Systems Engineering
Content type:
Blog
blog.ludovic.dev
·
4d
4 days ago
·
Hacker News
,
Hacker News
Actions for The Boot Chain of a RISC-V Board: From Silicon to Ubuntu 26.04
Red Hat Releases Second Developer Preview Of RHEL 10 For
RISC-V
🖥️
Bytecode VMs
phoronix.com
·
6h
6 hours ago
Actions for Red Hat Releases Second Developer Preview Of RHEL 10 For RISC-V
Vortex expands open
RISC-V
graphics
⚙️
Systems Engineering
jonpeddie.com
·
2d
2 days ago
Actions for Vortex expands open RISC-V graphics
Page 2 »
Log in to enable infinite scrolling
Keyboard Shortcuts
Navigation
Next / previous item
j
/
k
Open post
o
or
Enter
Preview post
v
Post Actions
Love post
a
Like post
l
Dislike post
d
Undo reaction
u
Save / unsave
s
Recommendations
Add interest / feed
Enter
Not interested
x
Go to
Home
g
h
Interests
g
i
Feeds
g
f
Likes
g
l
History
g
y
Changelog
g
c
Settings
g
s
Browse
g
b
Search
/
Pagination
Next page
n
Previous page
p
General
Show this help
?
Submit feedback
!
Close modal / unfocus
Esc
Press
?
anytime to show this help