💪 ARM Architecture - nmarshall · Scour

Finding and Understanding Bugs in FPGA Place-and-Route Engines [video] ⚡Hardware Acceleration

youtube.com·2d·Hacker News

Show HN: TiGrIS, a tiling compiler that fits ML models onto embedded devices 🚀MLOps

github.com·2d·Hacker News

The FPGA Milestone That Let Engineers Rewrite Chips Like Software 🔌FPGA

spectrum.ieee.org

·3d·Hacker News

What the DRAM Crunch Teaches Us About System Design 🧠Neuromorphic Chips

eetimes.com·3d·Hacker News, r/hardware

MemTensor/MemOperator-4B 🔁Cache Coherence

huggingface.co·4d·Hacker News

From Standards To Systems: The Chiplet Era On Arm 🏗️System Design

semiengineering.com·1d

Reimagining Kernel Generation at the PTX Layer: An LLM System Learning from DSLs to Outperform Them ⚙️LLVM

standardkernel.com·4d·Hacker News

PEAKS No 42: The Open-Weight Uprising: GPT-5.5, Qwen Beats a 397B Giant, and Your Jira Data Is Now AI Training Fuel ⚙️n8n

bogdandeac.com·3d

dmiller-fork/libkr: A library of the examples from the c programming language by Kernighan and Ritchie λFunctional Programming

github.com·4d·Hacker News

XiaomiMiMo/MiMo-V2.5-Pro 🤖AI Inference

huggingface.co·4d·Hacker News, r/LocalLLaMA

NoC Coherency Challenges Balloon With AI SoCs And Chiplets 🔁Cache Coherence

semiengineering.com·1d

Can a Chip That Loves Zeros Make Huge AI Models More Efficient? ⚡Hardware Acceleration

spectrum.ieee.org

·3d·Hacker News, r/hardware

Building An AI Chip: Silicon Design And Advanced Packaging ⚡Hardware Acceleration

semiengineering.com·2d

Microarchitecture Tailored to 3D-Stacked Near-Memory Processing LLM Decoding (U. of Edinburg, Peking U., Cambridge et al.) 🔁Cache Coherence

semiengineering.com·3d

New CPU Memory Module 🔁Cache Coherence

semiengineering.com·3d

XiaomiMiMo/MiMo-v2.5 🎚️Audio Codecs

huggingface.co·4d·Hacker News, Hacker News

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