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🔍 Chip Verification
RISC-V Testing, Hardware Validation, Formal Methods, SystemVerilog
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7656
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116.1
ms
Formal
Verification Fundamentals Remain
Non-Negotiable
In The New Verification Revolution
semiengineering.com
·
7h
🔌
FPGA
htfab/microlane
: Self-contained RTL to GDS flow for simple chip designs
github.com
·
16h
·
Discuss:
Hacker News
🔌
FPGA
Results from the
Advent
of
FPGA
Challenge
blog.janestreet.com
·
10h
·
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Hacker News
🔌
FPGA
Proof-oriented
Programming in F*
fstar-lang.org
·
10h
·
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Lobsters
λ
Functional Programming
Fidelity
Research
CS-2
a go-go 🫣
twogoodears.blogspot.com
·
2h
·
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Blogger
🛡️
Computer Security
[
TUHS
] bare m4 (was BTL
summmer
employees)
tuhs.org
·
23h
·
Discuss:
Lobsters
🦀
Rust Macros
Chiplets
And
3D-ICs
Add New Electrical And Mechanical Challenges
semiengineering.com
·
7h
⚡
Hardware Acceleration
Porting an INT8 VHDL CNN from Intel
Agilex
3 to Lattice
Certus-NX
news.ycombinator.com
·
1h
·
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Hacker News
💪
ARM Architecture
How I Used Claude Code to
Teach
Myself
Rust
mlolson.github.io
·
23h
·
Discuss:
Hacker News
,
r/programming
🦀
Rust Macros
I built a $15
ESP32
smart
clock
that does things no store-bought one can
xda-developers.com
·
15h
🔌
Microcontrollers
Stable
kernels
for Wednesday
lwn.net
·
1d
⚙
Risc-v
Formal
Methods
Practice and Theory
adacore.com
·
2d
·
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Hacker News
λ
Functional Programming
SAE
Feature Matchmaking (Layer-to-Layer) by
Mitali
M
greaterwrong.com
·
2d
📱
Edge AI
Building a
Regex
Engine with a team of parallel
Claudes
lesswrong.com
·
1d
⚙️
DataFusion
Show HN: We
achieved
72.2% issue resolution on
SWE-bench
Verified using AI teams
agyn.io
·
35m
·
Discuss:
Hacker News
🤖
AI Coding Tools
InfraBuilder
: The
Deterministic
Hardware Architect
dev.to
·
4d
·
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DEV
☁️
Serverless Rust
Testing a 6200 and
comparison
with 6100
68kmla.org
·
2d
⚙️
Performance Profiling
The RAM shortage finally
convinced
me to learn memory
overclocking
xda-developers.com
·
2h
💾
Cache Optimization
Zig
on small
SoC
(256KB)?
ziggit.dev
·
2d
⚙️
Zig
Emv
Helper
Tools
emv.works
·
2h
·
Discuss:
Hacker News
💻
CLI Tools
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