🏗 Computer Architecture - nmarshall · Scour

Microarchitecture Tailored to 3D-Stacked Near-Memory Processing LLM Decoding (U. of Edinburg, Peking U., Cambridge et al.) 🔁Cache Coherence

semiengineering.com·1d

Deep Moats and Platform Shifts in Computing ⚙Risc-v

semiconductor.substack.com·4d·Substack

What it takes to transpose a matrix (2024) ⚡SIMD Optimization

gudok.xyz·13h·Lobsters, Hacker News

My local agentic dev setup today 🤖AI agents

willemvandenende.com·1h·Hacker News

Building a browser VDJ deck with AI: 97% prompt cache rate, $1.2k in API spend 🎚️Audio Codecs

slerp.audio·1d·Hacker News

Claude Code Opus 4.7: 16B cache reads across 8 sessions, forensic JSONL data 🔁Cache Coherence

github.com·9h·Hacker News

Your CPU Has More Registers Than You'd Think ⚙️CPU Microarchitecture

fp32.org·6d·Lobsters, Hacker News

AutoSP: Long-Context LLM Training via Compiler-Based Sequence Parallelism 🔨Compilers

pytorch.org·21h·Hacker News

Evaluating CUDA Tile for AI Workloads on Hopper and Blackwell GPUs ⚡Hardware Acceleration

arxiv.org·2d·Hacker News

vnmoorthy/ccmeter: Local-first spend & cache-efficiency dashboard for Claude Code. Reads ~/.claude/projects, tells you exactly what's costing you. No telemetry, no API key. 📡OpenTelemetry

github.com·23h·Hacker News

You don't need an expensive GPU to run a local LLM that actually works 💻Local LLMs

xda-developers.com·1d

I made my C++ vector search engine 16x faster by changing data layout, not the algorithm ⚡SIMD Optimization

dubeykartikay.com·4d·Hacker News, r/cpp, r/programming

Reimagining Kernel Generation at the PTX Layer: An LLM System Learning from DSLs to Outperform Them ⚙️LLVM

standardkernel.com·2d·Hacker News

On Interaction Nets and Hardware 🧠Memory Models

tendrils.co·3d·Lobsters, Hacker News

This AMD processor crushes workloads at a price that finally makes sense ⚙️CPU Microarchitecture

xda-developers.com·1d

The FPGA Milestone That Let Engineers Rewrite Chips Like Software 🔌FPGA

spectrum.ieee.org

·1d·Hacker News

Mojo language, any hardware. Systems-level performance. Pythonic syntax 🧩WebAssembly

modular.com·6d·Hacker News

How to Choose Hardware for Running Local LLMs and Save Money 🧪Home Lab

madebyagents.com·2d·Hacker News

TSMC SoIC 3D stacking roadmap outlines path from 6-micron pitches today to 4.5-micron in 2029 — Fujitsu's Monaka CPU to benefit from face-to-face chiplet stacki... ⚡Hardware Acceleration

tomshardware.com

·1d·Hacker News

dogmaticdev/SIMD-Tokenizer: A Hyper Optimzed Tokenizer written in handwritten assembly. Made for SSE2 cpu architectures. 🔨Compilers

github.com·4d·Hacker News

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