Open Hardware, Chip Design, Embedded Systems, Computing Architecture

Writing an operating system kernel from scratch
popovicu.com·1d·
Risc-v
Automated DSL Optimization for Spiking Neural Network Hardware Synthesis
dev.to·1d·
Discuss: DEV
🧠Neuromorphic Chips
More hardware won’t fix bad engineering
infoworld.com·4h
Hardware Acceleration
486Tang – 486 on a credit-card-sized FPGA board
nand2mario.github.io·1d·
Discuss: Hacker News
Hardware Acceleration
A Lisp compiler to ARM written in Lisp (2)
forum.ulisp.com·26m·
Discuss: Hacker News
☁️Serverless Rust
5 reasons you need to be more careful with RAM on Ryzen
xda-developers.com·1d
🔌Embedded Rust
Disaggregated Inference at Scale with PyTorch and VLLM
pytorch.org·1d·
Discuss: Hacker News
🏗️AI Infrastructure
Refurb weekend: Silicon Graphics Indigo² IMPACT 10000
oldvcr.blogspot.com·1d·
Risc-v
Balance between refactoring and inheritance in your code
github.com·1h·
Discuss: Hacker News
🔍Static Analysis
4-bit Single Board Computer Based on the Intel 4004 Microprocessor
hackaday.com·3d·
Discuss: Hacker News
Risc-v
LLMs on a Shoestring: The Dynamic Cache Advantage by Arvind Sundararajan
dev.to·3h·
Discuss: DEV
💻Local LLMs
Beyond the Hype: Why Your AI Assistant Might Be Sabotaging Your Architecture
medium.com·7h·
Discuss: Hacker News
🧩Low-code
J-Link RTT for the Masses using Semihosting on ARM
bogdanthegeek.github.io·13h·
Discuss: Hacker News
🔌Embedded Rust
The future of microoptimization
goldenstack.net·2d·
Discuss: Hacker News
🔍Query Compilers
AMD Turin PSP binaries analysis from open-source firmware perspective
blog.3mdeb.com·15h·
Discuss: Hacker News
Risc-v
Review: SpikingBrain Technical Spiking Brain-Inspired Large Models
arxiviq.substack.com·2d·
Discuss: Substack
🧠Neuromorphic Chips
The Demise Of Static Timing Verification?
semiengineering.com·4d
🔍Chip Verification
Trigger crossbar
serd.es·19h·
Discuss: Hacker News
🔌Microcontrollers
Optimized Modbus RTU Data Validation via Hybrid Markov & Bayesian Filtering
dev.to·3h·
Discuss: DEV
🔍Chip Verification