Developing RISC-V Compute Subsystems
semiengineering.com·1d
⚙Risc-v
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Wireless Sensor Networks as Parallel and Distributed Hardware Platform for Artificial Neural Networks
arxiv.org·53m
🧠Neuromorphic Chips
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Unleash AI Performance: How Chiplets and Smart Networks Are Democratizing Custom Silicon by Arvind Sundararajan
⚡Hardware Acceleration
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Fil-C: A memory-safe C implementation
⚠️Unsafe Rust
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Extropic claims its new AI chip (TSU) is 10,000x more energy-efficient than GPUs
🧠Neuromorphic Chips
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resource driven design
arnau.bearblog.dev·2d
🌐Distributed systems
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Efficiency Defines The Future Of Data Movement
semiengineering.com·21h
💪ARM Architecture
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Raising the Bar on ML Model Deployment Safety
uber.com·15h
📱Edge AI
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AUTOSAR-Aligned Analysis Of 180 SoC Vulnerabilities In Auto Architecture (Chalmers, Univ. of Gothenburg)
semiengineering.com·1d
🔌Embedded Rust
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I upgraded my motherboard, and I didn't expect to love this part the most
xda-developers.com·17h
🖥computers
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Vectorizing for Fun and Performance
⚡SIMD Optimization
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Myths Programmers Believe about CPU Caches
🔌Embedded Rust
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Building a Rules Engine from First Principles
towardsdatascience.com·11h
λFunctional Programming
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Smart Handling Of Reset Domain Crossings To Non-Resettable Flip-Flops
semiengineering.com·21h
🔍Chip Verification
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Artificial neurons that replicate biological function for improved chips
🧠Neuromorphic Hardware
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All You Need for Object Detection: From Pixels, Points, and Prompts to Next-Gen Fusion and Multimodal LLMs/VLMs in Autonomous Vehicles
arxiv.org·53m
📱Edge AI
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