Skip to main content
Scour
Browse
Getting Started
Login
Sign Up
You are offline. Trying to reconnect...
Copied to clipboard
Unable to share or copy to clipboard
Computer Architecture
🏗️ Computer Architecture
CPU, instruction set, cache, microarchitecture, hardware
Filter Results
Timeframe
Fresh
Past Hour
Today
This Week
This Month
Feeds to Scour
Subscribed
All
Scoured
43
posts in
9.7
ms
Apple Chip
Architecture
from 1977 to 2026
🔩
Internals
Content type:
News
Content type:
Blog
blog.jacobstechtavern.com
·
19h
19 hours ago
Actions for Apple Chip Architecture from 1977 to 2026
The Return of Rigorous Full-System Timing Simulation
📊
Profiling Tools
sigarch.org
·
1d
1 day ago
·
Hacker News
Actions for The Return of Rigorous Full-System Timing Simulation
Elasticsearch simdvec deep-dive: Walking the
memory
tightrope to 2x better vector throughput
⚡
Performance
Content type:
Blog
elastic.co
·
5d
5 days ago
Actions for Elasticsearch simdvec deep-dive: Walking the memory tightrope to 2x better vector throughput
uiCA: Accurate Throughput
Prediction
of Basic Blocks on Recent Intel
Microarchitectures
⚡
Performance
Content type:
Academic
arxiv.org
·
12h
12 hours ago
·
Hacker News
Actions for uiCA: Accurate Throughput Prediction of Basic Blocks on Recent Intel Microarchitectures
Why x86 Zeroes a Register With `xor eax, eax`
⚙️
LLVM
Content type:
Blog
debasishg.github.io
·
2d
2 days ago
Actions for Why x86 Zeroes a Register With `xor eax, eax`
RISC-V profiles – why is RVA23 significant?
⚡
Performance
Content type:
Blog
ubuntu.com
·
6d
6 days ago
Actions for RISC-V profiles – why is RVA23 significant?
Intel 8086, the First x86 chip, Enters its 50th Year in 2027
🖥️
Systems Programming
techpowerup.com
·
1d
1 day ago
Actions for Intel 8086, the First x86 chip, Enters its 50th Year in 2027
Fractal OS Lets Security Researchers See What Their CPUs Really Do
⚡
Performance
Content type:
News
spectrum.ieee.org
·
23h
23 hours ago
Actions for Fractal OS Lets Security Researchers See What Their CPUs Really Do
Beyond the
Memory
Wall: The
CPU
Was Helping You All Along
⚡
Performance
Content type:
Blog
prawns.dev
·
3d
3 days ago
·
Hacker News
Actions for Beyond the Memory Wall: The CPU Was Helping You All Along
Building a MIPS emulator with Zig to replace MARS and QtSpim
🖥️
Systems Programming
ziggit.dev
·
6h
6 hours ago
Actions for Building a MIPS emulator with Zig to replace MARS and QtSpim
Sequential hardness of a MUL-XOR-shift permutation: open questions
⚙️
Compilers
Content type:
Code
github.com
·
1d
1 day ago
·
r/crypto
Actions for Sequential hardness of a MUL-XOR-shift permutation: open questions
How much do amd64
microarchitecture
levels help in Go?
⚡
Performance
Content type:
Blog
lemire.me
·
3d
3 days ago
·
Lobsters
,
Hacker News
,
r/golang
Actions for How much do amd64 microarchitecture levels help in Go?
How Will the AI IC Market Evolve Amid Rising Artificial Intelligence Adoption Through 2034?
💻
Software Engineering
Content type:
Blog
semiconinsights.blogspot.com
·
1h
1 hour ago
Actions for How Will the AI IC Market Evolve Amid Rising Artificial Intelligence Adoption Through 2034?
Exploiting GPU Tensor Cores from Java using Babylon [Juan Fumero]
🔩
Internals
openjdk.org
·
1d
1 day ago
·
r/java
Actions for Exploiting GPU Tensor Cores from Java using Babylon [Juan Fumero]
From Database and Virtualized Workloads to Backup: Dell PowerEdge R4715 and R5715 for SMB Realities
⚡
Performance
storagereview.com
·
4d
4 days ago
Actions for From Database and Virtualized Workloads to Backup: Dell PowerEdge R4715 and R5715 for SMB Realities
Two Leaps to 1000 Tokens/s on a 1T-Parameter Model: On Inference Systems, Execution Boundaries, and
Co-Design
⚡
Performance
Content type:
Blog
tilert.ai
·
1d
1 day ago
·
Hacker News
Actions for Two Leaps to 1000 Tokens/s on a 1T-Parameter Model: On Inference Systems, Execution Boundaries, and Co-Design
What Arm-based innovations happened in May 2026?
🔩
Internals
Content type:
Blog
newsroom.arm.com
·
4d
4 days ago
Actions for What Arm-based innovations happened in May 2026?
Founding Engineer - FPGA, RTL, & ASIC
Architect
at Zettascale
🖥️
Systems Programming
ycombinator.com
·
5d
5 days ago
·
Hacker News
Actions for Founding Engineer - FPGA, RTL, & ASIC Architect at Zettascale
RISC-V Summit Europe 2026: Industry and Academia Unite in Bologna to Advance Open
Hardware
🖥️
Systems Programming
Content type:
News
eetimes.com
·
1d
1 day ago
Actions for RISC-V Summit Europe 2026: Industry and Academia Unite in Bologna to Advance Open Hardware
AGENTSERVESIM: A
Hardware-aware
Simulator for Multi-Turn LLM Agent Serving
⚡
Performance
Content type:
Academic
arxiv.org
·
1d
1 day ago
Actions for AGENTSERVESIM: A Hardware-aware Simulator for Multi-Turn LLM Agent Serving
Page 2 »
Log in to enable infinite scrolling
Keyboard Shortcuts
Navigation
Next / previous item
j
/
k
Open post
o
or
Enter
Preview post
v
Post Actions
Love post
a
Like post
l
Dislike post
d
Undo reaction
u
Save / unsave
s
Recommendations
Add interest / feed
Enter
Not interested
x
Go to
Home
g
h
Interests
g
i
Feeds
g
f
Likes
g
l
History
g
y
Changelog
g
c
Settings
g
s
Browse
g
b
Search
/
Pagination
Next page
n
Previous page
p
General
Show this help
?
Submit feedback
!
Close modal / unfocus
Esc
Press
?
anytime to show this help