RISC-V International · Scour

Enabling High Performance RISC-V Software for AI in the Real World

7 Things I Learned at RISC-V Summit North America 2025

Andes: d-Matrix and Andes Team on World’s Highest Performing, Most Efficient Accelerator for AI Inference at Scale

EDN: RISC-V Summit spurs new round of automotive support

WebProNews: RISC-V’s ISO Milestone: Open ISA Poised for Global Dominance

We’re Showcasing RISC-V at SC25, the World’s Largest Supercomputing Conference

EEWorldOnline: MIPS releases multithreaded processor for edge computing

RISC-V International Names Tom Gall as Vice President of Technology

EDN: The next RISC-V processor frontier: AI

All About Circuits: Upbeat Technology’s RISC-V MCU Takes Flight With Near-Threshold Computing

EETimes: Google Open-Sources NPU IP, Synaptics Implements It

Introducing the RISCstar toolchain for RISC-V

RISC-V Takes First Step Toward International Standardization as ISO/IEC JTC1 Grants PAS Submitter Status

riscv.org·30w·Hacker News

The RISC-V Revolution: Insights from the 2025 Summits and Andes Technology’s Pivotal Role

RISC-V International to announce 25% market penetration

Ashling and Embecosm Extend PyTorch AI to RISC-V Embedded Devices

Optimizing Hardware for Neural Network Inference using Virtual Prototypes

Optimizing Hardware for Neural Network Inference using Virtual Prototypes

New Course Coming Soon: Porting Software to RISC-V (LFD 114)

Tom’s Hardware: RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing silicon footprint

Log in to enable infinite scrolling