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PCIe Design Guide – Q&A (Gen 4, 5, 6) – Part 2

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2025 – A Year Of Change And Anticipation

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Minimizing Design Risk: Rapid Feasibility Exploration For Multi-Die Designs

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Transforming Data Management In EDA: Preparing For The AI Era

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Programmable Chips Evolve For Shifting Needs

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LLM- Based Techniques To Support Behavior-Driven Development For HW Design (U. of Bremen, DFKI)

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Physical Modeling and Benchmarking for 2T-SOT-MRAM (Georgia Tech, MIT, Cornell)

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Thermal Modeling in Emerging Heterogeneous 2.5D/3D Systems (EPFL, Universidad Complutense de Madrid)

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Research Bits: Dec. 22

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Chip Industry Technical Paper Roundup: Dec 22

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Analysis of Thermal and Mechanical Behavior for Advanced Packaging (Sungkyunkwan Univ. et al)

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Data-Centric ML Compiler For PIM (U. of Toronto, Barcelona Supercomputing Center, ETH Zurich, Max Planck)

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Structural Integrity Assessment of IC Packaging Using Scanning Acoustic Microscopy (Arizona State Univ., Fraunhofer IMWS)

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Chip Industry Week in Review

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Multiple QPUs With Slow Interconnects Can Outperform Single QPU Monolithic Architecture (IonQ, Aalto Univ.)

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Unlocking Next-Gen Thermal Management: Why Indium-Based Metal TIMs Are Game-Changers

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Faster Mask Synthesis With GPUs

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Minimizing Voltage Loss And Improving Yield In Advanced GAA Chips

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Reliability Risks Shift To The Materials Stack

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What’s Next for 2.5D Packaging?

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