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D\'ej\`a Vu Packing: Optimizing FPGA Logic Clustering Runtime via Pattern Memoization  ⚙️Mechanical Sympathy
arxiv.org·2d
Tessera: Secure, Near-Line-Rate Weight Streaming for UMA Edge Accelerators  ⚡Hardware Acceleration
arxiv.org·2d
Hardware Generation and Exploration of Lookup Table-Based Accelerators for 1.58-bit LLM Inference  ⚡Hardware Acceleration
arxiv.org·1d
TetrisG-SDK: Efficient Convolutional Layer Mapping with Adaptive Windows and Grouped Convolutions for Fast In-Memory Computing  📦Batch Embeddings
arxiv.org·1d
Stochastic KV Routing: Enabling Adaptive Depth-Wise Cache Sharing  🧠Memory Hierarchy Design
arxiv.org·2d
Evaluating CUDA Tile for AI Workloads on Hopper and Blackwell GPUs  ⚡Hardware Acceleration
arxiv.org·2d·Hacker News
Noise-aware selection of circuit cutting strategies under hardware noise non-uniformity  🔬RaBitQ
arxiv.org·2d
Exploiting pre-optimized kernels with polyhedral transformations for CGRA compilation  🧮Compute Optimization
arxiv.org·3d
SimdQuickHeap: The QuickHeap Reconsidered  ⚡Vectorized Execution
arxiv.org·1d
A comprehensive evaluation of spatial co-execution on GPUs using MPS and MIG technologies  ⚡Hardware Acceleration
arxiv.org·3d
Microarchitectural Co-Optimization for Sustained Throughput of RISC-V Multi-Lane Chaining Vector Processors  🖥️Hardware Architecture
arxiv.org·3d
AutoINV: Automated Invariant Generation Framework for Formal Verification on High-Level Synthesis Designs  📐TLA+
arxiv.org·3d

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