💨 Cache-Friendly Algorithms - emschwartz · Scour

Set-Associative Caches: Trading Global Optimality for Predictable Speed 💾CPU Caching Blog

debasishg.github.io·4d

Less-relevant results

GreenGNN: Energy-Aware Windowed Communication Optimization for Distributed GNN Training 🎯Data Locality Academic

Every byte matters 💾CPU Caching

fzakaria.com·3d·Lobsters, Hacker News, Hacker News, r/programming

Zig Structs of Arrays (2024) ⚡Comptime Programming

andreashohmann.com·1d·Hacker News

HP has slashed an astonishing $2,600 off this RTX 5080 gaming PC, nearly 50% off — get an epic Omen 35L rig with a 9900X3D, 64GB DDR5, and 4TB of SSD storage for just $2,899.99 💾Disk I/O

tomshardware.com

·21h

gburd/libumem: This is the user space slab memory allocator, umem, first available in Solaris 9. (mirror of: codeberg.org/gregburd/libumem) 🧠Memory Allocators Code

AMD brought the Ryzen 7 5800X3D back because AM4 refuses to die 💾CPU Caching

pcworld.com·4d

I made a CPU only spiking neuron network lib that comes pretty close to PyTorch 💾CPU Caching

huggingface.co·6d·Hacker News

Uber caps AI usage 🚫, every byte matters 💾, containing Claude 👮 💻Claude Code

Redis 8.8 performance improvements: Faster string, hash, streams, SCAN & more 💾CPU Caching Blog

Dynamics and Representation Structure of Local Approximations to Gradient-Based Learning in Linear Recurrent Neural Networks 🎯Data Locality Academic

Light Cone Consistency: I'll Take One Scoop of Each 🌐Distributed systems Blog

swytchbv.substack.com·1d·Substack, r/programming, r/webdev

Shopify Reports 15X Faster Graphql Execution with Breadth First Engine 🔌API Design Theory

Computex 2026: AMD launches "new" Ryzen 5800X3D for AM4 and 7700X3D for AM5 🏭TSMC

(PR) MediaTek Collaborates with NVIDIA on RTX Spark to Power the Next Wave of Windows PC Experiences 💻Chips

techpowerup.com·3d

XCENA raises $135M for its computational memory controller 🧠Memory Hierarchy Design

siliconangle.com·6d

G116: Nanosecond-level hardware jitter detection on Linux 🔐Cryptography Code

github.com·6d·Hacker News

AMD EXPO ULL is intended to reduce DDR5 latencies on AM5 🧠Memory Hierarchy Design

igorslab.de·3d

Intel's 288-Core Clearwater Forest Xeon 6+ Lands on 18A, Claiming 30% Performance & 50% Efficiency Lead Over AMD's 192-Core EPYC (June 1 11 AM Taiwan) ⚡Systems Performance

wccftech.com·4d

Chain-of-Thought and Compressed Looped Transformers: A Memory-Budget Separation 🪄Prompt Engineering Academic

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