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🔁 Cache Coherence
Multi-Core, Memory Models, MESI Protocol, CPU Architecture
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Domestic Solutions for High-End Automotive Chips:
SiEngine
Breaks the
Deadlock
autonews.gasgoo.com
·
16h
🔌
Embedded Systems
A
crossbar
chip for benchmarking semiconductor spin
qubits
nature.com
·
16h
⚛️
Quantum Computing
Influence of component
arrangement
on thermal management in
immersion-cooled
server boards
sciencedirect.com
·
15h
🧩
Cache Partitioning
Anubis
OSS
— Local LLM Benchmarking for Apple Silicon
devpadapp.com
·
3d
·
Discuss:
r/opensource
⚙️
Performance Profiling
MPSpeed
: Implementing and Optimizing
MPC-in-the-Head
Digital Signatures in Hardware
eprint.iacr.org
·
3d
🚀
Superoptimization
Quick
Stack
Tiedown
artlu.bearblog.dev
·
1d
🏗️
Cranelift
Linux 7.0
MM
Changes Bring Some Very Nice Performance
Optimizations
phoronix.com
·
1h
📋
Zero-Copy
cysqlite
—a new
sqlite
driver
simonwillison.net
·
1d
🗄️
SQLite Internals
I Made a MCP for
Contextual
Memory for
IDE
's
dalexor.com
·
1d
·
Discuss:
r/SideProject
🧩
mimalloc
Optimizing the
MongoDB
Java Driver: How minor
optimizations
led to macro gains
linkedin.com
·
1d
·
Discuss:
DEV
📄
FlatBuffers
I did this instead of adding a metadata
vdev
to my
ZFS
pool, and everything got faster
xda-developers.com
·
8h
💾
ZFS
More details of an extra big Intel Nova Lake '
bLLC
' CPU die with added cache and designed to take on AMD's
X3D
chips emerge
pcgamer.com
·
1d
🔢
Intel AMX
AI
Inference
Needs A
Mix-And-Match
Memory Strategy
semiengineering.com
·
19h
🌊
Memory Bandwidth
Zprime137/iZprime
:
iZprime
, a study on algorithmic prime generation
github.com
·
6h
·
Discuss:
r/C_Programming
🧩
Mimalloc Internals
Intel "Nova Lake" Compute
Tile
Die-sizes
Surface
techpowerup.com
·
1d
🏗️
CPU Cache Topology
Memgraph
3.8 is Out: Atomic
GraphRAG
+ Vector Single Store With Major Performance Upgrades
memgraph.com
·
9h
·
Discuss:
Hacker News
🚀
Milvus
[News] SK
hynix
Unveils AI Chip Architecture with
HBF
, Reportedly Boosts Performance per Watt by Up to 2.69×
trendforce.com
·
1d
·
Discuss:
r/hardware
💾
HBM
Edge AI in a
DRAM
shortage
: Doing more with less
edn.com
·
17h
📱
Edge AI
From Buffers to Registers: Unlocking Fine-Grained
FlashAttention
with
Hybrid-Bonded
3D NPU Co-Design
arxiv.org
·
22h
🌊
Memory Bandwidth
Floating
bus
technical
guide
k1.spdns.de
·
12h
💭
Virtual Memory
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