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Memory Addressing and Memory Mapped I/O | by Tom Herbert | Jan, 2026
medium.com·2d
🗂️mmap
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Bringing Data Transformations Near-Memory for Low-Latency Analytics in HTAP Environments
arxiv.org·1d
📊Vectorized Query Execution
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Heaps do lie: debugging a memory leak in vLLM.
mistral.ai·16h·
Discuss: Hacker News
📊Cachegrind
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understanding LSM trees via read, write, and space amplification
bitsxpages.com·9h
🌲LSM Trees
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FastMCP 3.0
producthunt.com·1d
🗂️mmap
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datahaven-xyz/datahaven: An EVM compatible Substrate chain, powered by StorageHub and secured by EigenLayer
github.com·6h
🎚️Tiered Storage
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One ISA, Infinite Use Cases: RISC-V and the Road to Workload-Specific Silicon
riscv.org·12h
RISC-V
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SplittingSecrets: A Compiler-Based Defense for Preventing Data Memory-Dependent Prefetcher Side-Channels
arxiv.org·1d
🚀Software Prefetching
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This cheap adapter might solve your RAM crisis
xda-developers.com·8h
Intel TSX
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Streamlining CUB with a Single-Call API
developer.nvidia.com·10h
🧩mimalloc
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A Novel Side-channel Attack That Utilizes Memory Re-orderings (U. of Washington, Duke, UCSC et al.)
semiengineering.com·13h
🔄Hardware Transactional Memory
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ANN v3: 200ms p99 query latency over 100 billion vectors
turbopuffer.com·1d·
Discuss: Hacker News
🌊Memory Bandwidth
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#1 - Spot Problems Before Reading Any Code
dev.to·12h·
Discuss: DEV
🔓Binary Exploitation
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Build Your Own Key-Value Storage Engine—Week 6
read.thecoder.cafe·19h
#️⃣Hash Tables
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DiskCache: Disk Backed Cache — DiskCache 5.6.1 documentation
grantjenks.com·1d
💾Cache Design
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My games stopped crashing after I ran this tiny Windows tool
makeuseof.com·15h
🎮QEMU TCG
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Complexity of ArenaAllocator
ziggit.dev·1d
🏛️Region-Based Memory
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SHADOW: Simultaneous Multi-Threading Architecture with Asymmetric Threads
danglingpointers.substack.com·1d·
Discuss: Substack
🧵Lightweight Threads
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New Linux Patch Improved NVMe Performance +15% With CPU Cluster-Aware Handling
phoronix.com·1d·
Discuss: Hacker News
💽NVMe
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Weird RAM issue
68kmla.org·1d
🔄Memory Disambiguation
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