🧩 RISC-V - matmat · Scour

Optimising a Pipelined RISC-V Core: From Naive Pipeline to Near-Superscalar Performance ⚡CPU Microarchitecture

mummanajagadeesh.github.io·5d·Lobsters, Hacker News

A Full-Stack Performance Evaluation Infrastructure for 3D-DRAM-based LLM Accelerators 🖥️Hardware Architecture

arxiv.org·2d

789 KB Linux Without MMU on RISC-V (2023) 🧩RISC-V Assembly

popovicu.com·2d·Hacker News

Architecting Intelligence: The Rise of RISC-V CPUs in Agentic AI Infrastructure 🧲RISC-V Archaeology

semiwiki.com·3d

Building Local AI Video Generation Rig: A Hardware Breakdown ⚡Compression Hardware

hackster.io·2d

RISC-V 101 – what is it and what does it mean for Canonical? 🧲RISC-V Preservation

ubuntu.com·4d·Hacker News

Cracking the Code: Secure Debugging in Mixed-Signal SoCs 🔧Hardware Verification

hackernoon.com·1d

Algorithms for Modern Hardware 🎯Performance Proofs

en.algorithmica.org·3d·Hacker News

John Mashey on 64-bit computing (1991) 📊RISC-V Vectors

bourguet.org·3d·Lobsters, Hacker News

$2 WeAct CH32V006F8U6 Mini Core board features CH32V006 RISC-V MCU, supports 3.3V or 5V I/O voltage 🔌Single Board PC

cnx-software.com·6d

RISC-V Optimized strnlen Implementation For Linux 7.1 Yields Big Speed-Up 🚀RISC-V Vector

phoronix.com·3d

FILCO: Flexible Composing Architecture with Real-Time Reconfigurability for DNN Acceleration 🖥️Hardware Architecture

arxiv.org·2d

Lex-Col/Guardian-Angel-Protocol: Hardware-enforced AI confinement via ARMv9-A CCA. Shifting alignment from heuristic probability to architectural certainty. Features RME isolation, TCB reduction, and the "Deaf Warden" Oracle. Engineering deterministic shackles for stochastic models. 🔐RISC-V Cryptography

github.com·6d·Hacker News

RISC-V Has Momentum. The Real Question Is Who Can Deliver 🧲RISC-V Preservation

semiwiki.com·6d

High-Performance RK3568 SOM Module for Industrial and AI App 🖥️Hardware Architecture

hackster.io·3d

Arch: An AI-Native Hardware Description Language for Register-Transfer Clocked Hardware Design ⚡Circuit Verification

arxiv.org·4d

PHAROS: Pipelined Heterogeneous Accelerators for Real-time Safety-critical Systems With Deadline Compliance 🦀Embedded Rust

arxiv.org·4d

DeepStack: Scalable and Accurate Design Space Exploration for Distributed 3D-Stacked AI Accelerators ⚡CPU Microarchitecture

arxiv.org·5d

GTaP: A GPU-Resident Fork-Join Task-Parallel Runtime with a Pragma-Based Interface ⚡Parallel Computing

arxiv.org·4d

Probabilistic Tree Inference Enabled by FDSOI Ferroelectric FETs 🔧Hardware Verification

arxiv.org·4d

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