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RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification  ⚖️RISC-V Formal
arxiv.org·4d
An AI agent just designed a complete RISC-V CPU from scratch in 12 hours  ⚙️RISC-V Microcode
techspot.com·2d
SBI and the Full Boot Process (RISC-V)  🔧RISC-V Assembler
popovicu.com·4d
Building a RISC-V CPU Core (LFD111x) | Linux Foundation Education  🔧RISC-V Assembler
training.linuxfoundation.org·5d·Hacker News
Giving RISC-V 1024 registers for zkVMs  🧩RISC-V Assembly
leonardoalt.github.io·5d·Hacker News
Floating point fun on Cortex-M processors  🦾ARM Cortex-M
blog.adafruit.com·5d
Evaluating Computing Platforms for Sustainability: A Comparative Analysis of FPGAs against ASICs, GPUs, and CPUs  🔧FPGA Preservation
arxiv.org·2d
SPAC: Automating FPGA-based Network Switches with Protocol Adaptive Customization  🔍FPGA Verification
arxiv.org·1d
Efficient Batch Search Algorithm for B+ Tree Index Structures with Level-Wise Traversal on FPGAs  🌲B-tree Variants
arxiv.org·1d
EnergAIzer: Fast and Accurate GPU Power Estimation Framework for AI Workloads  📊Performance Profiling
arxiv.org·2d
Fresh Masking Makes NTT Pipelines Composable: Machine-Checked Proofs for Arithmetic Masking in PQC Hardware  🌊Stream Ciphers
arxiv.org·2d
A Comparative Analysis of ARM and x86-64 Laptop-Class Processors: Architecture, Assembly-Level Performance, and Energy Efficiency  🦾ARM Assembly
arxiv.org·3d
From Natural Language to Silicon: The Representation Bottleneck in LLM Hardware Design  ⚡Circuit Design
arxiv.org·4d
Idle is the New Sleep: Configuration-Aware Alternative to Powering Off FPGA-Based DL Accelerators During Inactivity  🖥️Hardware Architecture
arxiv.org·3d
Silicon Aware Neural Networks  🖥️Hardware Architecture
arxiv.org·3d
Overmind NSA: A Unified Neuro-Symbolic Computing Architecture with Approximate Nonlinear Activations and Preemptive Memory Bypass  📊Quantization
arxiv.org·5d
Different Perspectives of Memory System Simulation  🔩Systems Programming
arxiv.org·4d·Hacker News
HarmChip: Evaluating Hardware Security Centric LLM Safety via Jailbreak Benchmarking  🧪RISC-V Fuzzing
arxiv.org·4d
Energy Efficient LSTM Accelerators for Embedded FPGAs through Parameterised Architecture Design  🖥️Hardware Architecture
arxiv.org·3d
Spec2Cov: An Agentic Framework for Code Coverage Closure of Digital Hardware Designs  🔧Hardware Verification
arxiv.org·5d

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