Beating the L1 cache with value speculation (2021)
mazzo.li·5h·
Discuss: Lobsters
🔮Branch Predictors
CPU Cache-Friendly Data Structures in Go: 10x Speed with Same Algorithm
skoredin.pro·15h·
Discuss: Hacker News
⚡Cache Optimization
LLM Optimization Notes: Memory, Compute and Inference Techniques
gaurigupta19.github.io·5h·
Discuss: Hacker News
🗺️Region Inference
The Next Computing Revolution: Bringing Processing Inside Memory
computer.org·30m·
Discuss: Hacker News
🧠Memory Models
Rigorous Evaluation of Microarchitectural Side-Channels with Statistical Model Checking
arxiv.org·17h
📱Bytecode Design
The Best Performance Optimization Is Sometimes Changing Your Architecture
reddit.com·1d·
Discuss: r/webdev
🚀Code Motion
A Primer on Memory Consistency and Cache Coherence, Second Edition
link.springer.com·1d·
Discuss: r/programming
🧠Memory Models
Advanced Vulkan Rendering: Building a Modern Frame Graph and Memory Management System
dev.to·8h·
Discuss: DEV
🌊Dataflow Languages
Intel Details Core Options for "Nova Lake" and "Diamond Rapids" Xeon 7 Processors
techpowerup.com·4d
⚡Instruction Fusion
Beyond Von Neumann: Toward a unified deterministic architecture
venturebeat.com·1d
🤝Cooperative Threading
Optimizing queries by using observability
infoworld.com·9h
📈Query Optimization
Highly concurrent in-memory counter in GoLang
engineering.grab.com·21h
🧠Memory Models
What happened to Longcat models? Why are there no quants available?
huggingface.co·3h·
Discuss: r/LocalLLaMA
✨Gleam
Achieving 1.2 TB/s Aggregate Bandwidth by Optimizing Distributed Cache Network
juicefs.com·1d·
Discuss: Hacker News
🌍HTTP Servers
Measuring Reorder Buffer Capacity
blog.stuffedcow.net·3d·
Discuss: Lobsters, Hacker News
📝Register Allocation
Processor stuck on 0.54ghz
i.redd.it·1d·
Discuss: r/computers
🔮Branch Predictors
Why We Need SIMD
parallelprogrammer.substack.com·18h·
Discuss: Substack
🔀SIMD Programming
Predictive Coding Light
nature.com·21h
🗺️Region Inference
Inside the Chiplet Revolution: How Arm’s Compute Subsystems Platform is Democratizing Custom AI Silicon
newsroom.arm.com·6h
💾Allocator Design
Understanding the KV Cache (feat. Self-Attention)
dev.to·14h·
Discuss: DEV
🔄Subinterpreters