Symmetric MultiProcessing, Hyper-Threading and scheduling on Maestro
blog.lenot.re·11h
📦Portable Bytecode
LLMs on a Shoestring: The Dynamic Cache Advantage by Arvind Sundararajan
dev.to·9h·
Discuss: DEV
💾Cache Algorithms
Intel Core Ultra 3 205 Gets Early Review
techpowerup.com·4h
🔧RISC-V
The future of microoptimization
goldenstack.net·2d·
Discuss: Hacker News
🔬Nanopasses
Condor Technology To Fly “Cuzco” RISC-V CPU Into The Datacenter
nextplatform.com·3h·
Discuss: Hacker News
🔧RISC-V
Rowhammer: TRR on DDR5 DRAM has been broken
comsec.ethz.ch·2h·
Discuss: Hacker News
🏷️Memory Tagging
Semantic Dictionary Encoding
falvotech.com·4h·
Discuss: Hacker News
🗂️Type Indexing
AI hardware reimagined for lower energy use
techxplore.com·6h
🔌Microcontrollers
A Breadboard Computer in Three Chips
hackaday.com·2d
📦Compact Data
New Arm CPUs and GPUs Up to 45% Faster Double the Ray-Tracing Speed
geeky-gadgets.com·13h
💪ARM64 Backend
iTWire - The Risc-V architecture that can shape the future of computing
itwire.com·14h
🔧RISC-V
Building a Simple Stack-Based Virtual Machine in Go
blog.phakorn.com·12h·
📚Stack Data Structures
Muon for Improved Foundation Model Pretraining Data Efficiency
building.nubank.com·1h
📋JSON Parsing
Conquering the LLM Memory Wall: How to Run 2–4x Longer Contexts with a Single Line of Code
reddit.com·7h·
Discuss: r/LocalLLaMA
🗺️Region Inference
AMD Turin PSP binaries analysis from open-source firmware perspective
blog.3mdeb.com·21h·
Discuss: Hacker News
📊perf Tools
Identifying Divergences in HW Designs For High Performance Computing Workloads (LBNL et al.)
semiengineering.com·2h
Performance
Intel's new Core i5-110 appears identical to a 2020 Comet Lake chip
techspot.com·28m
🔮Speculative Execution
xmake-io/xmake
github.com·16h
🔗Language Toolchains
Disaggregated Inference at Scale with PyTorch and VLLM
pytorch.org·1d·
Discuss: Hacker News
🔄Subinterpreters