CPU Cache-Friendly Data Structures in Go: 10x Speed with Same Algorithm
skoredin.pro·4h·
Discuss: Hacker News
Cache Optimization
Rigorous Evaluation of Microarchitectural Side-Channels with Statistical Model Checking
arxiv.org·6h
📱Bytecode Design
A Primer on Memory Consistency and Cache Coherence, Second Edition
link.springer.com·17h·
Discuss: r/programming
🧠Memory Models
Here's Why RAM Should Be Your Priority When Buying a Laptop
howtogeek.com·12h
📏Linear Memory
Beyond Von Neumann: Toward a unified deterministic architecture
venturebeat.com·1d
🤝Cooperative Threading
Understanding the KV Cache (feat. Self-Attention)
dev.to·3h·
Discuss: DEV
🔄Subinterpreters
Highly concurrent in-memory counter in GoLang
engineering.grab.com·10h
🧠Memory Models
The Best Performance Optimization Is Sometimes Changing Your Architecture
reddit.com·23h·
Discuss: r/webdev
🚀Code Motion
Cuckoo hashing improves SIMD hash tables
reiner.org·1d·
🏗️Hash Tables
[NodeBook] Memory Fragmentation and Buffer Coding Challenges
thenodebook.com·2d·
Discuss: r/node
🏟️Arena Allocation
Why We Need SIMD
parallelprogrammer.substack.com·7h·
Discuss: Substack
🔀SIMD Programming
Leaker Clears The Air On Intel Core Ultra X Series, Models To Feature Full Xe3 iGPU
pokde.net·17h
🔧RISC-V
Startup Funding: Q3 2025
semiengineering.com·3h
🗺️Region Inference
Gabriele Bartolini: CNPG Recipe 22 - Leveraging the New Supply Chain and Image Catalogs
gabrielebartolini.it·22m
🗑️Stack Scanning GC
Simple LLM VRAM calculator for model inference
bestgpusforai.com·2d·
Discuss: Hacker News
🗺️Region Inference
Fun with HyperLogLog and SIMD
vaktibabat.github.io·2d·
🔢Bit Manipulation
The Role of AI in Next-Gen Chip Design
dev.to·10h·
Discuss: DEV
🔌Microcontrollers
Blogpost: A Mental Model for GPU Engineering for LLMs
modelcraft.substack.com·1d·
Discuss: Substack
🧠Memory Models
Locality, and Temporal-Spatial Hypothesis
brooker.co.za·1d
💾Persistent Heaps
Reflections on Designing a Search Autocomplete System
torontostudygroup.github.io·1d·
Discuss: DEV
🌿Trie Structures