⚙️ CPU Microarchitecture - hello · Scour

CPU-less parallel execution of lambda calculus in digital logic

arxiv.org·23h

🔓Lock-Free Programming

Pushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC-V Extension

semiwiki.com·1d

Show HN: BackBuild – A framework for sequencing complex software delivery

arcaned.co·17h·

Discuss: Hacker News

🏗️Cranelift

FlashAttention 4: Faster, Memory-Efficient Attention for LLMs

digitalocean.com·17h

🔄Hardware Transactional Memory

SHADOW: Simultaneous Multi-Threading Architecture with Asymmetric Threads

danglingpointers.substack.com·1d·

Discuss: Substack

🧵Lightweight Threads

Intel Bartlett Lake, P-Cores only: The leak Intel never wanted to comment on

igorslab.de·23h

🛡️Intel SGX

The Story on ISPC (Intel SPMD Program Compiler)

pharr.org·1d·

Discuss: Hacker News

Power-Efficient Processor Leverages Novel Dataflow Architecture

electronicdesign.com·2d·

Discuss: r/embedded

⚡Hardware Acceleration

Hardware-Aware Reformulation of Convolutions for Efficient Execution on Specialized AI Hardware: A Case Study on NVIDIA Tensor Cores

arxiv.org·23h

🔬Deep Learning

A Novel Side-channel Attack That Utilizes Memory Re-orderings (U. of Washington, Duke, UCSC et al.)

semiengineering.com·10h

🔄Hardware Transactional Memory

Intel axes 12th Gen Alder Lake and 4th Gen Xeon Sapphire Rapids — final orders for Intel's first hybrid CPUs end in just a few months

tomshardware.com

·11h·

Discuss: r/technews

Field Notes on Scaling MoE Expert Parallelism with DeepEP

nousresearch.com·1d·

Discuss: Lobsters

Subsystem many-hypercube codes: High-rate concatenated codes with low-weight syndrome measurements

link.aps.org·20h

📡Van Jacobson Channels

One ISA, Infinite Use Cases: RISC-V and the Road to Workload-Specific Silicon

riscv.org·9h

Scalable Adaptive Memory Compiler Optimization via Multi-Objective Evolutionary Algorithms

dev.to·1d·

Discuss: DEV

Memory Addressing and Memory Mapped I/O | by Tom Herbert | Jan, 2026

medium.com·2d

Arctic Wolf’s Liquid Clustering Architecture Tuned for Petabyte Scale

databricks.com·10h

🎚️Tiered Storage

ANN v3: 200ms p99 query latency over 100 billion vectors

turbopuffer.com·1d·

Discuss: Hacker News

🌊Memory Bandwidth

Cadence Unveils Tensilica HiFi iQ DSP Purpose-Built for Next-Generation Voice AI and Audio Applications

audioxpress.com·8h

Computer-on-Modules for an efficient entry into rugged embedded edge AI applications

einpresswire.com·1d

🔌Embedded Systems

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