🏗 Computer Architecture - hello · Scour

Algorithms for Modern Hardware 🔀SIMD Programming

en.algorithmica.org·5d·Hacker News

Question - CPU Microarchitecture Thread ⚙️CPU Microarchitecture

forums.anandtech.com·26m

Building Redstone: A cache optimized for high throughput AI workloads 🎴TAO

eventual-consistency.vercel.app·2d·r/rust

Quantization Dominates Rank Reduction for KV-Cache Compression 📦Succinct Data Structures

arxiv.org·17h

Towards O(1) Computing: Minimizing System Entropy with Data-Centric High-Frequency Processing ⚙️Systems Programming

dev.to·1d·DEV

The Hidden Value of CPU-Intensive Compression on Modern Hardware 🌊Memory Bandwidth

klarasystems.com·6d

Visualizing CPU Pipelining (2024) ⚙️CPU Microarchitecture

timmastny.com·1d·Hacker News

PipeSC: A Resource-efficient and Pipelined Hardware Accelerator for Sumcheck Protocol ⚙️CPU Microarchitecture

eprint.iacr.org·6d

Architecting Intelligence: The Rise of RISC-V CPUs in Agentic AI Infrastructure 🧩mimalloc

semiwiki.com·5d

RISC-V 101 – what is it and what does it mean for Canonical? ⚡RISC-V

ubuntu.com·6d·Hacker News

CUTEv2: Unified and Configurable Matrix Extension for Diverse CPU Architectures with Minimal Design Overhead ⚡Hardware Acceleration

arxiv.org·17h

Tracking down a 25% Regression on LLVM RISC-V 🔨LLVM

blog.kaving.me·5d·Lobsters, Hacker News

EdgeCIM: A Hardware-Software Co-Design for CIM-Based Acceleration of Small Language Models 🧠PIM

arxiv.org·17h

IceCache: Memory-efficient KV-cache Management for Long-Sequence LLMs 🎴TAO

arxiv.org·17h

PG-MDP: Profile-Guided Memory Dependence Prediction for Area-Constrained Cores 🎲Hardware Branch Prediction

arxiv.org·4d

A Full-Stack Performance Evaluation Infrastructure for 3D-DRAM-based LLM Accelerators 🌊Memory Bandwidth

arxiv.org·4d

TRAPTI: Time-Resolved Analysis for SRAM Banking and Power Gating Optimization in Embedded Transformer Inference 🎲Hardware Branch Prediction

arxiv.org·5d

POS-ISP: Pipeline Optimization at the Sequence Level for Task-aware ISP 🔗Link-Time Optimization

arxiv.org·5d

Arch: An AI-Native Hardware Description Language for Register-Transfer Clocked Hardware Design 🎲Hardware Branch Prediction

arxiv.org·6d

KV Cache Offloading for Context-Intensive Tasks 🧱Slab Allocation

arxiv.org·4d

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