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🏗 Computer Architecture
RISC-V, Pipelining, Cache Optimization, Microcode
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144113
posts in
27.2
ms
The
RISC
Concept - A Survey of
Implementations
inf.fu-berlin.de
·
11h
⚙️
CPU Microarchitecture
Utility-Based Cache
Partitioning
: Making Shared
Caches
Smarter in Multi-Core Systems
dev.to
·
17h
·
Discuss:
DEV
🧩
Cache Partitioning
Hardware
footprint
benchmarks for an offline
maps/routing/geocoding
stack
corviont.com
·
1h
·
Discuss:
Hacker News
🚀
Performance
μpack
: Faster & more flexible
integer
compression
blog.cf8.gg
·
1d
·
Discuss:
r/programming
,
r/rust
📏
Run-Length Encoding
Build your soft
Risc-V
with
XO4
in no time
hackster.io
·
6h
⚡
RISC-V
Can One Chip
Contort
Itself to
Accelerate
All Applications?
spectrum.ieee.org
·
1d
·
Discuss:
r/technews
⚡
Hardware Acceleration
InnerQ
: Hardware-aware Tuning-free Quantization of
KV
Cache for Large Language Models
arxiv.org
·
1d
📊
Profile-Guided Optimization
I designed an
MMU-less
5-stage RISC-V CPU entirely with Generative AI (With full
debug
support & verification)
github.com
·
1d
·
Discuss:
r/embedded
⚡
RISC-V
Deep Dive: How
StarRocks
Built a High-Performance
Vectorized
Engine
starrocks.io
·
3d
⏩
SIMD
Petter
Reinholdtsen
: Free software toolchain for the simplest RISC-V CPU in a small FPGA?
hungry.com
·
17h
⚡
RISC-V
Intel mobile CPUs have achieved up to 95x performance uplift over the past two decades — benchmarking the gains from
45nm
Penryn
to 18A Panther Lake
tomshardware.com
·
19h
🎯
Intel IPP
DualPath
: Breaking the Storage
Bandwidth
Bottleneck in Agentic LLM Inference
mesuvash.github.io
·
14h
·
Discuss:
Hacker News
🌊
Memory Bandwidth
Claude Skills and
Subagents
: Escaping the Prompt Engineering
Hamster
Wheel
towardsdatascience.com
·
29m
💬
Prompt Engineering
RISC-V
Linux will be ready for wide adoption in 2026, says
Canonical
howtogeek.com
·
23h
📏
Picolibc
Building two-dimensional
microprocessors
with a
foundry-inspired
strategy
nature.com
·
2d
⚡
Hardware Acceleration
Simulating the IBM 360/50
mainframe
from its
microcode
righto.com
·
11h
🔀
SIMD Programming
Researchers double AI training speeds by taming long-tail
inefficiencies
in processor
utilization
notebookcheck.net
·
19h
💬
Prompt Engineering
akalinux/orderedmap
: A very fast Sorted Map for go
github.com
·
9h
·
Discuss:
r/golang
🗺️
BTreeMap
Scaling
with Speed
stories.rivian.com
·
22h
🚀
Performance
(PR)
Supermicro
Introduces Industry's Highest Density AMD EPYC 4005 Series
MicroBlade
for Cloud, Edge, and SaaS Workloads
techpowerup.com
·
2d
🛡️
Intel SGX
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