🏗 Computer Architecture - hello · Scour

MagiCache: A Virtual In-Cache Computing Engine ⚡Cache Optimization

danglingpointers.substack.com·10h·Substack

Algorithms for Modern Hardware 🔀SIMD Programming

en.algorithmica.org·5d·Hacker News

Question - CPU Microarchitecture Thread ⚙️CPU Microarchitecture

forums.anandtech.com·1h

Building Redstone: A cache optimized for high throughput AI workloads 🎴TAO

eventual-consistency.vercel.app·2d·r/rust

Interferences within a certifiable design methodology for high-performance multi-core platforms 🧵OpenMP

arxiv.org·18h

Microsecond Latency in a Managed Language: The Performance Philosophy Behind Typhon 🌲Splay Trees

nockawa.github.io·2d

The Hidden Value of CPU-Intensive Compression on Modern Hardware 🌊Memory Bandwidth

klarasystems.com·6d

Visualizing CPU Pipelining (2024) ⚙️CPU Microarchitecture

timmastny.com·1d·Hacker News

Building Redstone: A cache optimized for high throughput AI workloads 🎴TAO

works-on-my-machine-eight.vercel.app·3d

PipeSC: A Resource-efficient and Pipelined Hardware Accelerator for Sumcheck Protocol ⚙️CPU Microarchitecture

eprint.iacr.org·6d

RISC-V 101 – what is it and what does it mean for Canonical? ⚡RISC-V

ubuntu.com·6d·Hacker News

Quantization Dominates Rank Reduction for KV-Cache Compression 📦Succinct Data Structures

arxiv.org·18h

From Characterization to Microarchitecture: Designing an Elegant and Reliable BFP-Based NPU 🎲Hardware Branch Prediction

arxiv.org·18h

CUTEv2: Unified and Configurable Matrix Extension for Diverse CPU Architectures with Minimal Design Overhead ⚡Hardware Acceleration

arxiv.org·18h

EdgeCIM: A Hardware-Software Co-Design for CIM-Based Acceleration of Small Language Models 🧠PIM

arxiv.org·18h

PG-MDP: Profile-Guided Memory Dependence Prediction for Area-Constrained Cores 🎲Hardware Branch Prediction

arxiv.org·4d

A Full-Stack Performance Evaluation Infrastructure for 3D-DRAM-based LLM Accelerators 🌊Memory Bandwidth

arxiv.org·4d

TRAPTI: Time-Resolved Analysis for SRAM Banking and Power Gating Optimization in Embedded Transformer Inference 🎲Hardware Branch Prediction

arxiv.org·5d

POS-ISP: Pipeline Optimization at the Sequence Level for Task-aware ISP 🔗Link-Time Optimization

arxiv.org·5d

Arch: An AI-Native Hardware Description Language for Register-Transfer Clocked Hardware Design 🎲Hardware Branch Prediction

arxiv.org·6d