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SHADOW: Simultaneous Multi-Threading Architecture with Asymmetric Threads
danglingpointers.substack.com·1d·
Discuss: Substack
🧵Lightweight Threads
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The Non-Predictability of Mispredicted Branches using Timing Information
arxiv.org·1d
🎲Hardware Branch Prediction
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AI Systems Performance Engineering
github.com·7h·
Discuss: Hacker News
🧩mimalloc
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A Novel Side-channel Attack That Utilizes Memory Re-orderings (U. of Washington, Duke, UCSC et al.)
semiengineering.com·13h
🔄Hardware Transactional Memory
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One ISA, Infinite Use Cases: RISC-V and the Road to Workload-Specific Silicon
riscv.org·12h
RISC-V
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FlashAttention 4: Faster, Memory-Efficient Attention for LLMs
digitalocean.com·20h
🔄Hardware Transactional Memory
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CPU-less parallel execution of lambda calculus in digital logic
arxiv.org·1d
🔓Lock-Free Programming
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Phase-space engineering and collective dynamics in memcomputing
link.aps.org·55m
🎴SIMD Shuffles
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Why FPGA Programmes Fail Late and Why Tool Choice Is Rarely the Real Issue
dev.to·1d·
Discuss: DEV
🔌FPGA Programming
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CAP Theorem Explained: Beyond the "Pick Two" Myth
blog.ahmazin.dev·1h·
Discuss: Hacker News
🔺CAP Theorem
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Extensible Scheduler Class — The Linux Kernel documentation
docs.kernel.org·2d
📅Linux Scheduling
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Clockworker: single-threaded async executor with powerful scheduling to sit on top of async runtimes
github.com·2d·
Discuss: r/rust
Tokio Runtime
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Streamlining CUB with a Single-Call API
developer.nvidia.com·10h
🧩mimalloc
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(PUBLIC) Building a better Go linker
docs.google.com·19h·
Discuss: Hacker News
🔗Link-Time Optimization
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Field Notes on Scaling MoE Expert Parallelism with DeepEP
nousresearch.com·1d·
🚀Intel ISPC
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Real-Time Data Stream Processing in Go: Backpressure, Windowing, and Fault Tolerance Explained
dev.to·18h·
Discuss: DEV
Timely Dataflow
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Power-Efficient Processor Leverages Novel Dataflow Architecture
electronicdesign.com·2d·
Discuss: r/embedded
Hardware Acceleration
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Intel axes 12th Gen Alder Lake and 4th Gen Xeon Sapphire Rapids — final orders for Intel's first hybrid CPUs end in just a few months
tomshardware.com
·15h·
Discuss: r/technews
Intel TSX
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Taking the axe to AI
newelectronics.co.uk·20h
📱Edge AI
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Adjusting One Line Of Linux Code Yields 5x Wakeup Latency Reduction For Modern Xeon CPUs
phoronix.com·21h
🛡️Intel CET
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