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Lock Management Inside a Process: Why Native Locks Alone Are Not Enough
dev.to·10h·
Discuss: DEV
🔒Futex
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Chain-of-Memory: Lightweight Memory Construction with Dynamic Evolution for LLM Agents
arxiv.org·47m
🔄Memory Ordering
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understanding LSM trees via read, write, and space amplification
bitsxpages.com·6h
🌲LSM Trees
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A Novel Side-channel Attack That Utilizes Memory Re-orderings (U. of Washington, Duke, UCSC et al.)
semiengineering.com·11h
🔄Hardware Transactional Memory
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Hippocampus model implementing a Turing machine
pub.towardsai.net·1h
🔲Cellular Automata
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SplittingSecrets: A Compiler-Based Defense for Preventing Data Memory-Dependent Prefetcher Side-Channels
arxiv.org·1d
🚀Software Prefetching
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Basic Memory
basicmemory.com·2d
🔄Memory Ordering
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Heaps do lie: debugging a memory leak in vLLM.
mistral.ai·14h·
Discuss: Hacker News
📊Cachegrind
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Agentic Memory
dolthub.com·5h
🔲Cellular Automata
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SHADOW: Simultaneous Multi-Threading Architecture with Asymmetric Threads
danglingpointers.substack.com·1d·
Discuss: Substack
🧵Lightweight Threads
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32GB of RAM costs $300 now: How to survive without upgrading
howtogeek.com·1d
🧠Memory Management
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FlashAttention 4: Faster, Memory-Efficient Attention for LLMs
digitalocean.com·18h
🔄Hardware Transactional Memory
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Arctic Wolf’s Liquid Clustering Architecture Tuned for Petabyte Scale
databricks.com·11h
🎚️Tiered Storage
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One ISA, Infinite Use Cases: RISC-V and the Road to Workload-Specific Silicon
riscv.org·10h
RISC-V
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Uncovering Unfaithful CoT in Deceptive Models
lesswrong.com·3h
🛡️AI Security
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Scalable Adaptive Memory Compiler Optimization via Multi-Objective Evolutionary Algorithms
dev.to·1d·
Discuss: DEV
🧩mimalloc
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The Impersistence of Memory
cacm.acm.org·5d
🚧Memory Barriers
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The Evolution of Redis: From Cache to AI-Database (V1.0 to 8.4)
percona.com·16h
🐉DragonflyDB
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Conversation: LLMs and the what/how loop
martinfowler.com·15h
⚙️Systems Programming
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Scientific Computing in Rust Monthly #14
scientificcomputing.rs·17h
🦀Rust Macros
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