Acquire-Release, Sequential Consistency, Relaxed Memory Models, Atomic Semantics

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A Novel Side-channel Attack That Utilizes Memory Re-orderings (U. of Washington, Duke, UCSC et al.)
semiengineering.com·5h
🔄Hardware Transactional Memory
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Reduction for Structured Concurrent Programs
arxiv.org·18h
🔓Lock-Free Programming
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Lock Management Inside a Process: Why Native Locks Alone Are Not Enough
dev.to·3h·
Discuss: DEV
🔒Futex
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Scalable Adaptive Memory Compiler Optimization via Multi-Objective Evolutionary Algorithms
dev.to·21h·
Discuss: DEV
🧩mimalloc
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Heaps do lie: debugging a memory leak in vLLM.
mistral.ai·8h·
Discuss: Hacker News
📊Cachegrind
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FlashAttention 4: Faster, Memory-Efficient Attention for LLMs
digitalocean.com·11h
🔄Hardware Transactional Memory
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32GB of RAM costs $300 now: How to survive without upgrading
howtogeek.com·1d
🧠Memory Management
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Memory Addressing and Memory Mapped I/O | by Tom Herbert | Jan, 2026
medium.com·2d
🗂️mmap
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understanding LSM trees via read, write, and space amplification
bitsxpages.com·30m
🌲LSM Trees
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One ISA, Infinite Use Cases: RISC-V and the Road to Workload-Specific Silicon
riscv.org·3h
RISC-V
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SplittingSecrets: A Compiler-Based Defense for Preventing Data Memory-Dependent Prefetcher Side-Channels
arxiv.org·18h
🚀Software Prefetching
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Key Value Memory In The Brain
pub.towardsai.net·23h
🧠Memory Models
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istmarc/tenseur: C++23 Tensor, neural networks and mathematical library
github.com·5h·
Discuss: r/cpp
⚙️XLA
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SHADOW: Simultaneous Multi-Threading Architecture with Asymmetric Threads
danglingpointers.substack.com·1d·
Discuss: Substack
🧵Lightweight Threads
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On rebuilding read models, Dead-Letter Queues and Why Letting Go is Sometimes the Answer
event-driven.io·2d·
Discuss: r/programming
💳Transactional Memory
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Guide to designing and testing memory for AI agents
theevalloop.substack.com·1d·
Discuss: Substack
🧩mimalloc
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Streamlining CUB with a Single-Call API
developer.nvidia.com·2h
🧩mimalloc
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Memory layout matters: Reducing metric storage overhead by 4x in a Rust TSDB
baarse.substack.com·8h·
Discuss: r/rust
🏛️Region-Based Memory
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Don't Trip[wire] Yourself: Testing Error Recovery in Zig
mitchellh.com·23h
⚙️Zig
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Dealing with alternatives
jemarch.net·1d
🏷️Pointer Tagging
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