Circuit Design

⚡ Circuit Design

Logic Synthesis, Hardware Description Languages, Digital Electronics, Circuit Verification

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Scoured 57 posts in 14.7 ms

StepPRM-RTL: Stepwise Process-Reward Guided LLM Fine-Tuning for Enhanced RTL Synthesis

 ⚙️Logic Synthesis  Content type: Academic
arxiv.org·

Subversion-Resistance for Free from Formal Verification

 🌐NetworkProtocols
lesswrong.com·

geohot/fromthetransistor: From the Transistor to the Web Browser, a rough outline for a 12 week course

 ⚙️Logic Synthesis  Content type: Code
github.com··Hacker News

MMO-CHIP: From Microscope to Verilog in an hour

 🔬Binary Analysis  Content type: Video
media.ccc.de··Lobsters

Giulio Zausa's MMO-CHIP Makes Reverse Engineering Old Silicon Chips a Multiplayer Game

 ⚡Circuit Archaeology  Content type: News
hackster.io·

Founding Engineer - FPGA, RTL, & ASIC Architect at Zettascale

 ⚙️Logic Synthesis
ycombinator.com··Hacker News

Disturbance In Verification

 🔍FPGA Verification
semiengineering.com·

From PAL to Verilog: Writing the A4092 Logic from Scratch (amiga.technology)

 ⚙️Logic Synthesis  Content type: Blog
amiga.technology·

Zcash Developers Weigh New Shielded Pool After Orchard Bug

 💻Programming languages
cointelegraph.com·

AMD ships second-gen Versal Prime accelerators

 ⚙️Logic Synthesis
networkworld.com·

OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design

 ⚙️Logic Synthesis  Content type: Academic
arxiv.org·

Exploring the Classic Xilinx XC5202-6PQ100I FPGA

 ⚙️Logic Synthesis
hackster.io·

Show HN: AutoGPU – AI designs a real 7nm GPU, from Verilog to GDSII

 ⚙️Logic Synthesis  Content type: Code
github.com··Hacker News

MMO-CHIP: From Microscope to Verilog in an hour (gpn24)

 ⚙️Logic Synthesis
cdn.media.ccc.de·

RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models

 🔧Hardware Verification  Content type: Academic
arxiv.org·

ROSUM-MCTS: Monte Carlo Tree Search-Inspired HDL Code Summarization with Structural Rewards

 ⚙️Logic Synthesis  Content type: Academic
arxiv.org·

Release metis: v1.4.0 · arm/metis

 ⚙️Logic Synthesis  Content type: Code
github.com·

Programming Domain-Specific FPGA Hardblocks from HLS: An RTL Blackbox Approach

 ⚙️Logic Synthesis  Content type: Academic
arxiv.org·

Formal verification of the S-two AIR

 💻Programming languages  Content type: Academic
arxiv.org·

Abduction Prover in Isabelle/HOL

 👑Isabelle/HOL  Content type: Academic
arxiv.org·

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