🔍 FPGA Verification - matmat · Scour

Understanding Inference-Time Token Allocation and Coverage Limits in Agentic Hardware Verification 🔧Hardware Verification

Spotting Specification Gaps with Small Proof-Oriented Tests ⚔️Lean Tactics

risemsr.github.io·4d·Hacker News

A-IC3: Learning-Guided Adaptive Inductive Generalization for Hardware Model Checking 🔧Hardware Verification

Evaluating Computing Platforms for Sustainability: A Comparative Analysis of FPGAs against ASICs, GPUs, and CPUs 🔧FPGA Preservation

SPAC: Automating FPGA-based Network Switches with Protocol Adaptive Customization ⚡Circuit Verification

SpecSyn: LLM-based Synthesis and Refinement of Formal Specifications for Real-world Program Verification ⚖️Verification Calculi

Exploring LLM-based Verilog Code Generation with Data-Efficient Fine-Tuning and Testbench Automation 🔧Hardware Verification

Stateful Embedded Fuzzing with Peripheral-Accurate SystemC Virtual Prototypes 🧪RISC-V Fuzzing

Structural Verification for Reliable EDA Code Generation without Tool-in-the-Loop Debugging 🔧Hardware Verification

Fresh Masking Makes NTT Pipelines Composable: Machine-Checked Proofs for Arithmetic Masking in PQC Hardware 🌊Stream Ciphers

Co-Designing Error Mitigation and Error Detection for Logical Qubits ⚛️Quantum Error Correction

From Finite Enumeration to Universal Proof: Ring-Theoretic Foundations for PQC Hardware Masking Verification ⚡Circuit Verification

VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation ⚡Circuit Verification

Spec2Cov: An Agentic Framework for Code Coverage Closure of Digital Hardware Designs 🔧Hardware Verification

HELIX: Verified compilation of cyber-physical control systems to LLVM IR ⚖️RISC-V Formal

Idle is the New Sleep: Configuration-Aware Alternative to Powering Off FPGA-Based DL Accelerators During Inactivity 🖥️Hardware Architecture

Verification Modulo Tested Library Contracts ⚖️Verification Calculi

Tractable Verification of Model Transformations: A Cutoff-Theorem Approach for DSLTrans ✅Format Verification

Clover: A Neural-Symbolic Agentic Harness with Stochastic Tree-of-Thoughts for Verified RTL Repair 🔧Hardware Verification

VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog 🧪Binary Fuzzing

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