🔧 RISC-V Assembler - matmat

2 to 4 cents Fortior FU75xx dual-core motor control MCU family combines 32-bit RISC-V core with 2nd-gen Motor Engine (ME2) core - CNX Software

🔌Microcontrollers News

cnx-software.com·

InjectV: Modeling Fault Injection Attacks in RISC-V Simulation Environment

🔍RISC-V Forensics Academic

arxiv.org·

The Boot Chain of a RISC-V Board: From Silicon to Ubuntu 26.04

👑RISC-V Privilege Blog

blog.ludovic.dev··Hacker News, Hacker News

Less-relevant results

coherentforge/CambiOS: Zero-trust, capability-based Rust microkernel targeting formal verification. Tri-arch (x86_64 / AArch64 / RISC-V). Sovereign and generative: no telemetry, user owns keys and data. Early-stage — see STATUS.md. Inspired by seL4, Hubris, and Redox.

👑RISC-V Privilege Code

github.com··Hacker News

The MilkV Jupiter 2/SpacemiT K3

⚙️Modern Assembly

taoofmac.com··Hacker News, Hacker News·Cited by 1 article

Red Hat Releases Second Developer Preview Of RHEL 10 For RISC-V

🧩RISC-V Assembly

phoronix.com·

Centurion: Bring Your Own Execution Environment

🔤DSLs Blog

praetorian.com·

Lua.ex: Sandboxed Lua 5.3 on the Beam, Built for AI Agents

💻programming languages

deflua.com··Hacker News

Automatia Update: Unbalanced Skills | RISC-V sandbox

⚙️Modern Assembly Blog

libriscv.no··Hacker News

IDA 9.4 Beta Is Now Available

🔬Binary Analysis Blog

hex-rays.com·

RISC-V Summit Europe 2026: Industry and Academia Unite in Bologna to Advance Open Hardware

🧲RISC-V Archaeology News

eetimes.com·

Linux 7.2 To Enable ESWIN SoC Support By Default For RISC-V Kernel Builds

🧩RISC-V

phoronix.com·

OpenCV 5 release - New DNN engine with enhanced ONNX and LLM/VLM support, Intel, Arm, and RISC-V hardware optimizations - CNX Software

⚙️Modern Assembly News

cnx-software.com·

RISC-V CPU Performance Up 8x In Five Years: SiFive HiFive Unmatched To SpacemiT K3

🧩RISC-V

phoronix.com·

Linux 7.2 Features Expected: Apple M3, Initial AMDGPU HDMI 2.1 FRL, USB4STREAM, Cache Aware Scheduling

💻Operating System, OS

phoronix.com·

Vortex 3.0 Released As Full-Stack, Open-Source RISC-V GPU Now With 3D Pipeline

🧩RISC-V

phoronix.com··Cited by 1 article

OpenCV 5.0 Released With Rewritten DNN Engine, Built-In LLM & VLM Support

📊RISC-V Vectors

phoronix.com··Hacker News·Cited by 1 article

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Fedora 44 RISC-V Images Released, Including New "Omni" Kernel For Broader RISC-V Hardware Support

RISC-V Targets Data Centers, Edge AI, Space

"RISC-V Is Now"

2 to 4 cents Fortior FU75xx dual-core motor control MCU family combines 32-bit RISC-V core with 2nd-gen Motor Engine (ME2) core - CNX Software

InjectV: Modeling Fault Injection Attacks in RISC-V Simulation Environment

The Boot Chain of a RISC-V Board: From Silicon to Ubuntu 26.04

coherentforge/CambiOS: Zero-trust, capability-based Rust microkernel targeting formal verification. Tri-arch (x86_64 / AArch64 / RISC-V). Sovereign and generative: no telemetry, user owns keys and data. Early-stage — see STATUS.md. Inspired by seL4, Hubris, and Redox.

The MilkV Jupiter 2/SpacemiT K3

Red Hat Releases Second Developer Preview Of RHEL 10 For RISC-V

Centurion: Bring Your Own Execution Environment

Lua.ex: Sandboxed Lua 5.3 on the Beam, Built for AI Agents

Automatia Update: Unbalanced Skills | RISC-V sandbox

IDA 9.4 Beta Is Now Available

RISC-V Summit Europe 2026: Industry and Academia Unite in Bologna to Advance Open Hardware

Linux 7.2 To Enable ESWIN SoC Support By Default For RISC-V Kernel Builds

OpenCV 5 release - New DNN engine with enhanced ONNX and LLM/VLM support, Intel, Arm, and RISC-V hardware optimizations - CNX Software

RISC-V CPU Performance Up 8x In Five Years: SiFive HiFive Unmatched To SpacemiT K3

Linux 7.2 Features Expected: Apple M3, Initial AMDGPU HDMI 2.1 FRL, USB4STREAM, Cache Aware Scheduling

Vortex 3.0 Released As Full-Stack, Open-Source RISC-V GPU Now With 3D Pipeline

OpenCV 5.0 Released With Rewritten DNN Engine, Built-In LLM & VLM Support