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💾 Cache Optimization
CPU Cache, Memory Hierarchy, Cache Lines, Prefetching
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Performance Tip of the Week #62:
Identifying
and reducing memory
bandwidth
needs
abseil.io
·
5h
⚙️
Performance Profiling
Clearing
caches
artima.com
·
5h
🧠
Memory Management
Enhancement
on
Caching
and Service Workers
dev.to
·
10h
·
Discuss:
DEV
💎
Redis
Concurrency
Deep Dive: Memory Models, Lock-Free, and
RCU
dev.to
·
13h
·
Discuss:
DEV
🧠
Memory Models
KV-CoRE: Benchmarking Data-Dependent Low-Rank
Compressibility
of
KV-Caches
in LLMs
arxiv.org
·
1d
🔁
Cache Coherence
How
WebAssembly
and Web Workers prevent UI
freezes
thenewstack.io
·
10h
🕸️
WASM
Performance
Tip
of the Week #7: Optimizing for application
productivity
abseil.io
·
5h
⚙️
Performance Profiling
More
cores
didn't improve my
workflow
xda-developers.com
·
4h
⚙️
CPU Microarchitecture
google/flatbuffers
:
FlatBuffers
: Memory Efficient
Serialization
Library
github.com
·
1d
🛡️
Memory Safety
Profiling
Go programs with
pprof
jvns.ca
·
3h
📊
Profiling
Stratum
: Architecting a
Configurable
Cache Simulator with C++ and Racket
thecloudlet.github.io
·
6d
·
Discuss:
Hacker News
🏗
Computer Architecture
Benchmarking
Malloc
with Doom 3
forrestthewoods.com
·
5h
📊
Profiling
The Risk of Not
Optimizing
Clock
Power
semiwiki.com
·
1d
⚙️
CPU Microarchitecture
How To Go
Slow
artima.com
·
5h
🛡️
Memory Safety
How I
squeezed
a
BERT
sentiment analyzer into 1GB RAM on a $5 VPS
mohammedeabdelaziz.github.io
·
12h
·
Discuss:
Hacker News
⚡
Ruff
I Built a 6
BIPS
JIT
in Five Months
unlikelyemphasis.substack.com
·
1d
·
Discuss:
Substack
⚙️
JIT Compilation
Hardware
Acceleration
jellyfin.org
·
7h
🖥️
Emulation
SPPAM
: Signature Pattern Prediction and Access-Map
Prefetcher
arxiv.org
·
2d
🔁
Cache Coherence
CUDA
Guide:
Workflow
for Performance Tuning
digitalocean.com
·
3d
⚙️
Performance Profiling
MicroBlaze
MCS Seven-Segment Counter on
Basys
3 FPGA
hackster.io
·
11h
🏗
Computer Architecture
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