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🏗 Computer Architecture
RISC-V, Pipelining, Cache Optimization, Microcode
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Performance Tip of the Week #62:
Identifying
and reducing memory
bandwidth
needs
abseil.io
·
10h
⚙️
Performance Profiling
MicroBlaze
MCS Seven-Segment Counter on
Basys
3 FPGA
hackster.io
·
17h
⚡
RISC-V
Efficiency
and Performance
dev.to
·
19h
·
Discuss:
DEV
⚙️
Systems Programming
Performance
Tip
of the Week #7: Optimizing for application
productivity
abseil.io
·
10h
⚙️
Performance Profiling
CVA6-CFI
: A First Glance at RISC-V Control-Flow Integrity Extensions
arxiv.org
·
2d
⚡
RISC-V
I Built a 6
BIPS
JIT
in Five Months
unlikelyemphasis.substack.com
·
2d
·
Discuss:
Substack
⚙️
JIT Compilation
Gathering
Scattered
I/O in C++
artima.com
·
10h
📋
Zero-Copy
More
cores
didn't improve my
workflow
xda-developers.com
·
10h
⚙️
CPU Microarchitecture
Portable
C
Compiler
en.wikipedia.org
·
9h
·
Discuss:
Hacker News
🔤
C Programming
KV-CoRE: Benchmarking Data-Dependent Low-Rank
Compressibility
of
KV-Caches
in LLMs
arxiv.org
·
2d
🔁
Cache Coherence
Show HN:
LocalGPT
– A local-first AI assistant in Rust with
persistent
memory
news.ycombinator.com
·
4h
·
Discuss:
Hacker News
🦀
Rust Macros
The Launch of
RISC-V
Now! A New
Chapter
in Open Computing
semiwiki.com
·
3d
⚡
RISC-V
CUDA
Guide:
Workflow
for Performance Tuning
digitalocean.com
·
3d
⚙️
Performance Profiling
Benchmarking
Malloc
with Doom 3
forrestthewoods.com
·
10h
📊
Profiling
What should I program?
jamesmcm.github.io
·
16m
🔨
Compiler Design
Last Week on My Mac: Why E
cores
make Apple
silicon
fast
eclecticlight.co
·
1h
⚙️
CPU Microarchitecture
InfraBuilder
: The
Deterministic
Hardware Architect
dev.to
·
1h
·
Discuss:
DEV
⚙️
CPU Microarchitecture
Hardware
Acceleration
jellyfin.org
·
13h
🖥️
Emulation
Hello Edge: Keyword
Spotting
on
Microcontrollers
paperium.net
·
1d
·
Discuss:
DEV
⚙️
CPU Microarchitecture
Memory-Safe
Jule
language
emerges
as C/C++ alternative
thenewstack.io
·
17h
🔬
Static Analysis
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