Semiconductor Engineering semiengineering.com

From Silos to Systems, from Data to Insight

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Building An AI Chip: Silicon Design And Advanced Packaging

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Microarchitecture Tailored to 3D-Stacked Near-Memory Processing LLM Decoding (U. of Edinburg, Peking U., Cambridge et al.)

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Rethinking ESD Protection for System-On-Integrated Chiplets (UC Riverside)

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Alumina Nanowires Improve Thermal Management in Advanced Packaging (Georgia Tech et al.)

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Mapping and Routing Fault-Tolerant Quantum Circuits Onto Chiplet Architectures (TU Munich)

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Leveraging Agentic AI Techniques to Improve Formal Verification (Infineon, et al.)

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Reflectometry-Based Technique for Characterising Complex Thin-Film Structures (Aalto U. et al.)

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New CPU Memory Module

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Research Bits: Apr. 28

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When Semiconductor Materials Misbehave

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TSMC Tech Symposium 2026, By The Numbers

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Chip Industry Week In Review

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System-in-Package Challenges

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Can Edge AI Keep Up?

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Blog Review: Apr. 22

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TSV Complexity Leads To Manufacturing Bottleneck

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Chip Industry Technical Paper Roundup: Apr. 21

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Research Bits: Apr. 21

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Why Proof Convergence Matters

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