Skip to main content
Scour
Browse
Getting Started
Login
Sign Up
You are offline. Trying to reconnect...
Close
You're currently offline. Some features may not work.
Close
Copied to clipboard
Close
Unable to share or copy to clipboard
Close
💾 Cache Algorithms
LRU, Cache Coherence, Memory Hierarchy, Performance
Filter Results
Timeframe
Fresh
Past Hour
Today
This Week
This Month
Feeds to Scour
Subscribed
All
Scoured
122053
posts in
1.56
s
Staying
on Top in the Age of LLMs
andrasgerlits.medium.com
·
15h
·
Discuss:
Hacker News
,
r/programming
🎮
Language Ergonomics
Carnegie
Mellon at
NeurIPS
2025
blog.ml.cmu.edu
·
1d
🪜
Recursive Descent
remote
locks
and
distributed
locks
tautik.me
·
1d
🎯
Ring Buffers
How High Can
Micron
Go In the Memory
Supercycle
? Here's What History Says
finance.yahoo.com
·
1d
🔗
Memory Linearization
The 4
Parameter-Efficient
Fine-Tuning Methods: How to
Adapt
LLMs 100× Faster
pub.towardsai.net
·
2d
🪜
Recursive Descent
Results from the
Advent
of
FPGA
Challenge
blog.janestreet.com
·
18h
·
Discuss:
Hacker News
🔄
Nanopass
Intel Nova Lake-S: When mainstream suddenly
smells
like
HEDT
igorslab.de
·
1d
⚡
Instruction Fusion
Beyond
Kuramoto
Models: Associative Memory and Plastic
Synapses
in ML Ensembles
hackernoon.com
·
1d
🗺️
Region Polymorphism
Our testing shows the Ryzen 7 9800X3D can match the
pricier
Ryzen 7 9850X3D with simple
PBO
settings — AMD's latest CPU can't leverage extra clock speed in game...
tomshardware.com
·
1d
·
Discuss:
r/hardware
🏗️
CPU Architecture
The
Datacenter
as a Computer: An Introduction to the Design of
Warehouse-Scale
Machines, Second Edition
research.google
·
2d
·
Discuss:
Hacker News
📁
File Systems
Functional
Optics
for Modern Java
blog.scottlogic.com
·
22h
✨
Gleam
Influence of component
arrangement
on thermal management in
immersion-cooled
server boards
sciencedirect.com
·
10h
⚡
Instruction Fusion
OLIX
: Compute
Manifesto
olix.com
·
1d
·
Discuss:
Hacker News
📡
Erlang BEAM
How
Andrej
Karpathy
Built a Working Transformer in 243 Lines of Code
analyticsvidhya.com
·
9h
🪜
Recursive Descent
Intel "Nova Lake" Compute
Tile
Die-sizes
Surface
techpowerup.com
·
1d
📱
Bytecode Design
Predicting Future Utility: Global
Combinatorial
Optimization for Task-Agnostic KV Cache
Eviction
arxiv.org
·
2d
🔮
CPU Branch Prediction
Two Ways to Move
Tensors
Without Stopping: Inside
vLLM
's Async GPU Transfer Patterns
dev.to
·
1d
·
Discuss:
DEV
💾
Zero-Copy
[
TUHS
] bare m4 (was BTL
summmer
employees)
tuhs.org
·
1d
·
Discuss:
Lobsters
🔀
Control Structures
MPSpeed
: Implementing and Optimizing
MPC-in-the-Head
Digital Signatures in Hardware
eprint.iacr.org
·
3d
⏲️
Embedded GC
More details of an extra big Intel Nova Lake '
bLLC
' CPU die with added cache and designed to take on AMD's
X3D
chips emerge
pcgamer.com
·
1d
🔮
Speculative Execution
Loading...
Loading more...
« Page 5
•
Page 7 »
Keyboard Shortcuts
Navigation
Next / previous item
j
/
k
Open post
o
or
Enter
Preview post
v
Post Actions
Love post
a
Like post
l
Dislike post
d
Undo reaction
u
Recommendations
Add interest / feed
Enter
Not interested
x
Go to
Home
g
h
Interests
g
i
Feeds
g
f
Likes
g
l
History
g
y
Changelog
g
c
Settings
g
s
Browse
g
b
Search
/
Pagination
Next page
n
Previous page
p
General
Show this help
?
Submit feedback
!
Close modal / unfocus
Esc
Press
?
anytime to show this help