Skip to main content
Scour
Browse
Getting Started
Login
Sign Up
You are offline. Trying to reconnect...
Close
You're currently offline. Some features may not work.
Close
Copied to clipboard
Close
Unable to share or copy to clipboard
Close
🔁 Cache Coherence
Multi-Core, Memory Models, MESI Protocol, CPU Architecture
Filter Results
Timeframe
Fresh
Past Hour
Today
This Week
This Month
Feeds to Scour
Subscribed
All
Scoured
112383
posts in
528.9
ms
Execution-Centric Characterization of
FP8
Matrix Cores, Asynchronous Execution, and Structured Sparsity on AMD
MI300A
arxiv.org
·
1d
⚙️
Performance Profiling
Minimum
Energy Per
Query
semiengineering.com
·
22h
⏪
Deoptimization
AI in Multiple
GPUs
: Understanding the Host and Device
Paradigm
towardsdatascience.com
·
17h
🔥
PyTorch
[Development] 4MB 32-bit
SRAM
for the
MicroMac
Performer
68kmla.org
·
6h
🔄
Hardware Transactional Memory
Cache-aware
disaggregated
inference for up to 40% faster long-context LLM
serving
together.ai
·
2d
·
Discuss:
Hacker News
,
r/LocalLLaMA
🎴
TAO
Intel Posts 2026 Update For
Cache
Aware
Scheduling
On Linux
phoronix.com
·
8h
📅
Linux Scheduling
Discussion - Investigation of Single Thread CPU "
Thoughput/cycle
"
forums.anandtech.com
·
1d
⚙️
Performance Profiling
C++20 matching engine - arena allocator, lock-free
SPSC
, intrusive linked lists, 255ns
p50
latency
github.com
·
51m
·
Discuss:
r/cpp
⚙️
LMAX Architecture
DRAMPyML
: A Formal Description of DRAM Protocols with Timed
Petri
Nets
arxiv.org
·
1d
🧠
Memory Models
Supercharging
Inference for AI Factories: KV Cache
Offload
as a Memory-Hierarchy Problem
blog.min.io
·
15h
🧱
Slab Allocation
How I Built
MemCP
:
Giving
Claude a Real Memory
dev.to
·
1d
·
Discuss:
DEV
💾
PMem Programming
Abhinnavverma/Telescope-Distributed-Log-Search-Engine
: A high-throughput, distributed log search engine built in Go. Featuring
LSM-tree
storage, hybrid caching, and custom inverted indexing.
github.com
·
2h
·
Discuss:
r/golang
🎴
TAO
A
RISC-V
vector
extension primer
blog.adafruit.com
·
14h
📏
Picolibc
TileIR
ianbarber.blog
·
1d
·
Discuss:
Hacker News
🌀
Naiad
Intelligent
Memory Launches a New Generation of
eMMC
for Industrial Applications
einpresswire.com
·
16h
💾
PMem Programming
How Memory Technology Is
Powering
the Next Era of
Compute
semiwiki.com
·
1d
🔄
Hardware Transactional Memory
Unleashing Computational Power: Ultimate Latency Optimization of Qwen3 and
Qwen3-VL
on AMD
MI300X
Series
lmsys.org
·
2d
🧩
mimalloc
Introduction To
Concurrency
|
Concurrency
Interview |
AlgoMaster.io
algomaster.io
·
1d
🔄
Concurrency
Intel Nova Lake Compute
Tile
Die Sizes Leak Highlighting Massive
L3
Cache Expansion
hothardware.com
·
15h
🏗️
CPU Cache Topology
AI
Inference
Needs A
Mix-And-Match
Memory Strategy
semiengineering.com
·
22h
🌊
Memory Bandwidth
Loading...
Loading more...
Page 2 »
Keyboard Shortcuts
Navigation
Next / previous item
j
/
k
Open post
o
or
Enter
Preview post
v
Post Actions
Love post
a
Like post
l
Dislike post
d
Undo reaction
u
Recommendations
Add interest / feed
Enter
Not interested
x
Go to
Home
g
h
Interests
g
i
Feeds
g
f
Likes
g
l
History
g
y
Changelog
g
c
Settings
g
s
Browse
g
b
Search
/
Pagination
Next page
n
Previous page
p
General
Show this help
?
Submit feedback
!
Close modal / unfocus
Esc
Press
?
anytime to show this help