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🔁 Cache Coherence
Multi-Core, Memory Models, MESI Protocol, CPU Architecture
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112425
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757.0
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Execution-Centric Characterization of
FP8
Matrix Cores, Asynchronous Execution, and Structured Sparsity on AMD
MI300A
arxiv.org
·
1d
⚙️
Performance Profiling
Minimum
Energy Per
Query
semiengineering.com
·
23h
⏪
Deoptimization
AI in Multiple
GPUs
: Understanding the Host and Device
Paradigm
towardsdatascience.com
·
18h
🔥
PyTorch
[Development] 4MB 32-bit
SRAM
for the
MicroMac
Performer
68kmla.org
·
8h
🔄
Hardware Transactional Memory
Cache-aware
disaggregated
inference for up to 40% faster long-context LLM
serving
together.ai
·
2d
·
Discuss:
Hacker News
,
r/LocalLLaMA
🎴
TAO
Intel Posts 2026 Update For
Cache
Aware
Scheduling
On Linux
phoronix.com
·
10h
📅
Linux Scheduling
Discussion - Investigation of Single Thread CPU "
Thoughput/cycle
"
forums.anandtech.com
·
1d
⚙️
Performance Profiling
Breaking the
Tractability
Barrier: A Generic Low-Level Solver for
NP-Hard
Instances (N=63) on Commodity 64-Bit Silicon
zenodo.org
·
1h
·
Discuss:
r/programming
🌀
Naiad
C++20 matching engine - arena allocator, lock-free
SPSC
, intrusive linked lists, 255ns
p50
latency
github.com
·
2h
·
Discuss:
r/cpp
⚙️
LMAX Architecture
DRAMPyML
: A Formal Description of DRAM Protocols with Timed
Petri
Nets
arxiv.org
·
1d
🧠
Memory Models
Supercharging
Inference for AI Factories: KV Cache
Offload
as a Memory-Hierarchy Problem
blog.min.io
·
16h
🧱
Slab Allocation
How I Built
MemCP
:
Giving
Claude a Real Memory
dev.to
·
1d
·
Discuss:
DEV
💾
PMem Programming
Abhinnavverma/Telescope-Distributed-Log-Search-Engine
: A high-throughput, distributed log search engine built in Go. Featuring
LSM-tree
storage, hybrid caching, and custom inverted indexing.
github.com
·
3h
·
Discuss:
r/golang
🎴
TAO
How Memory Technology Is
Powering
the Next Era of
Compute
semiwiki.com
·
1d
🔄
Hardware Transactional Memory
A
RISC-V
vector
extension primer
blog.adafruit.com
·
16h
📏
Picolibc
Unleashing Computational Power: Ultimate Latency Optimization of Qwen3 and
Qwen3-VL
on AMD
MI300X
Series
lmsys.org
·
2d
🧩
mimalloc
Avalue
EMX-PTLP
– A thin mini-ITX motherboard powered by up to an Intel Core Ultra 7
358H
Panther Lake-H SoC
cnx-software.com
·
11m
📡
Intel PMT
TileIR
ianbarber.blog
·
1d
·
Discuss:
Hacker News
🌀
Naiad
Introduction To
Concurrency
|
Concurrency
Interview |
AlgoMaster.io
algomaster.io
·
1d
🔄
Concurrency
Intel Nova Lake Compute
Tile
Die Sizes Leak Highlighting Massive
L3
Cache Expansion
hothardware.com
·
16h
🏗️
CPU Cache Topology
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